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參數(shù)資料
| 型號： | GS9000CCPJ |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Serial Digital Decoder |
| 中文描述： | 串行數(shù)字解碼器 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 106K |
| 代理商： | GS9000CCPJ |
5
522 - 49 - 01
G
R
EXT
C
EXT
SWC
EXTERNAL
COMPONENTS
V
DD
V
DD
6k8
Fig. 5 Pin 15 SWC
Fig. 6 Pins 3, 16, 17, 19 - 25, 27, 28
SWF, HSYNC, SSI, SSD, PCLK, PD0-9
Fig. 7 Waveforms
In order to maintain very short interconnections when
interfacing with the GS9005A Receiver, the critical high
speed inputs such as Serial Data (pins 5 and 6) and Serial
Clock (pins 7 and 8) are located along one side of the device
package.
If the automatic standard select function is not used, the
Standard Select bits (pins 9 and 10) do not need to be
connected, however the control input (pin 11) should be
grounded.
TEST SET-UP & APPLICATION INFORMATION
Figure 8 shows the test set-up for the GS9000C operating
from a V
DD
supply of +5 volts. The differential pseudo ECL
inputs for DATA and CLOCK (pins 5,6,7 and 8) must be
biased between +3.0 and +4.0 volts. In the circuit shown,
these inputs with the resistor values shown, can be directly
driven from the outputs of the GS9005A Reclocking Receiver.
In other cases, such as true ECL level driver outputs, two
biasing resistors are needed on the DATA and CLOCK inputs
and the signals must be AC coupled.
It is critical that the decoupling capacitors connected to pins
12,13 and 18 be chip types and be located as close as
possible to the device pins.
GND
OUTPUT
V
DD
t
SU
t
HOLD
t
CLKL
=
t
CLKH
SERIAL
CLOCK
(SCI)
SERIAL
DATA
(SDI)
50%
PARALLEL
DATA
(PDn)
50%
PARALLEL
CLOCK
(PCLK)
1/2
T
1/2
T
t
D
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS9000CCPJ-E3 | 制造商:Gennum 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS9000CCTJ | 制造商:Gennum Corporation 功能描述: |
| GS9000-CPJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SMPTE |
| GS9000CPTJE3 | 制造商:Gennum Corporation 功能描述: |
| GS9000D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:270Mb/s Deserializer for use with GS7025. GS9025A or GS9035A. |
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