參數(shù)資料
型號(hào)： GS9000CCPJ
廠(chǎng)商： Electronic Theatre Controls, Inc.
英文描述： Serial Digital Decoder
中文描述： 串行數(shù)字解碼器
文件頁(yè)數(shù)： 7/8頁(yè)
文件大?。?/td> 106K
代理商： GS9000CCPJ
7
522 - 49 - 01
G
Figure 11 shows an application of the GS9000C in an
adjustment free, multi-standard serial to parallel convertor.
This circuit uses the GS9010A Automatic Tuning Sub-system
IC and a GS9005A Serial Digital Receiver. The GS9005A may
be replaced with a GS9015A Reclocker IC if cable equalization
is not required.
The GS9010A ATS eliminates the need to manually set or
externally temperature compensate the Receiver or Reclocker
VCO. The GS9010A can also determine whether the incoming
data stream is 4sc NTSC,4sc PAL or component 4:2:2.
The GS9010A includes a ramp generator/oscillator which
repeatedly sweeps the Receiver/Reclocker VCO frequency
over a set range until the system is correctly locked. An
automatic fine tuning (AFT) loop maintains the VCO control
voltage at its centre point through continuous, long term
adjustments of the VCO centre frequency.
During normal operation, the GS9000C Decoder provides
continuous HSYNC pulses which disable the ramp/oscillator
of the GS9010A. This maintains the correct Receiver/
Reclocker VCO frequency. When an interruption to the incoming
data stream is detected by the Receiver/Reclocker, the
Carrier Detect goes LOW and tri-states the AFT loop in order
to maintain the correct VCO frequency for a period of about
2 seconds. This allows the Receiver/Reclocker to rapidly
relock when the signal is re-established.
GS9000C, GS9005A and GS9010A INTERCONNECTIONS
Fig. 11 Application Circuit - Adjustment Free Multi-standard Serial to Parallel Convertor
STANDARD TRUTH TABLE
/2 P/N STANDARD
0 0 4:2:2 - 270
0 1 4:2:2 - 360
1 0 4sc - NTSC
1 1 4sc - PAL
P/N
OUT
IN-
COMP
LF
/2
V
CC
SWF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PARALLEL DATA BIT 9
PARALLEL DATA BIT 8
PARALLEL DATA BIT 7
PARALLEL DATA BIT 6
PARALLEL DATA BIT 5
PARALLEL DATA BIT 4
PARALLEL DATA BIT 3
PARALLEL DATA BIT 2
PARALLEL DATA BIT 1
PARALLEL DATA BIT 0
PARALLEL CLOCK OUT
SYNC CORRECTION ENABLE
HSYNC OUTPUT
SYNC WARNING FLAG
INPUT SELECTION
STDT
V
CC
CD
HSYNC
GND
OSC
DLY
FVCAP
10
μ
+
10
μ
10
μ
+
+
V
CC
+5V
+5V
V
CC
V
CC
V
CC
0
μ
1
100
100
100
100
390
390
390
390
0
μ
1
0
μ
1
0
μ
1
25
24
23
22
21
20
19
5
6
7
8
9
10
11
4 3 2 1 28 27 26
V
C
1
12 13 14 15 16 17 18
910
22n(1)
(2)
(2)
(2)
(3)
75
113
75
47p
5p6
10n
0
μ
1
0
μ
1
3n3
82n
180n
0
μ
68
0
μ
1
22n
DGND
DGND
DGND
DGND
47p
0
μ
1
DGND
GND
1k2
1k2
68k
100 100
120
50k
0.1
μ
100k
SWF
GS9010A
INPUT
ECL
DDI
DDI
V
CC2
SDI
SDI
/2
V
EE3
SDO
SDO
SCO
SCO
SS1
SS0
CD
V
E
A
A
S
V
E
V
C
L
R
V
R
V
R
V
E
O
R
V
V
C
25
24
23
22
21
20
19
5
6
7
8
9
10
11
4 3 2 1 28 27 26
V
S
0
μ
1
DGND
DGND
SSI
100
100
100
100
100
100
3k3
100
100
100
100
GS9000C
SDI
SDI
SCI
SCI
SS1
SS0
SSC
DV
CC
PD7
PD6
PD5
PD4
PD3
PD2
PD1
V
D
S
V
S
H
P
P
V
S
V
D
V
D
12 13 14 15 16 17 18
S
S
P
P
STAR
V
CC
V
CC
V
CC
V
CC
6
μ
8
6
μ
8
+
+
GS9005A
V
CC
V
CC
DV
CC
DV
CC
V
CC
DV
CC
V
CC
SWF
(1) Typical value for input return loss matching
(2) To reduce board space, the two anti-series 6.8
μ
F capacitors (connected across pins 2 and 3 of the GS9010A)
may be replaced with a 1.0
μ
F non-polarized capacitor provided that
(a) the 0.68
μ
F capacitor connected to the OSC pin (11) of the GS9010A is replaced with a 0.33
μ
F capacitor and
(b) the GS9005A /15A Loop Filter Capacitor is 10nF.
(3) Remove this potentiometer if P/N function is not required, and ground pin 16 of the GS9010A.
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