參數(shù)資料
型號： GS9023-CFY
廠商： Electronic Theatre Controls, Inc.
英文描述： Aluminum Electrolytic Radial Leaded Bi-Polar Capacitor; Capacitance: 100uF; Voltage: 63V; Case Size: 12.5x20 mm; Packaging: Bulk
中文描述： 嵌入式音頻編解碼器
文件頁數(shù)： 22/33頁
文件大?。?/td> 301K
代理商： GS9023-CFY
GENNUM CORPORATION
522 - 45 - 05
22
G
MULTIPLEX AND DEMULTIPLEX MODES
Delay of Video and Audio
The GS9023 can be configured for various audio sample
delays with respect to the video signal. The audio sample
delay is selected in
“
BUFSEL[1:0]
”
of Host Interface
Register #6h. Table 13 lists the various audio sample
delays.
Host Interface
The Host Interface Registers allow for device configuration
and provide status information. The GS9023 contains
sixteen internal registers that are accessible through the
Host Interface. Based on the mode of operation the
registers have different functionality. In Multiplex Mode the
registers are defined in Table 14 and in Demultiplex Mode
the registers are defined in Table 15.
The asynchronous Host Interface consists of a 4 bit address
bus (ADDR[3:0]), 8 bit data bus (DATA[7:0]), read enable
(RE), write enable (WE) and chip select (CS). The Host
Interface access is independent of the PCLK or ACLK
inputs. Read and write cycle timing is detailed in Figure 16.
In a read cycle, CS is driven LOW t
AS
seconds after a valid
address. RE is then driven LOW after t
ACS
seconds for a
minimum of t
RD
seconds. After t
GQV
seconds, the address
register contents are output on the data bus. After a
minimum of t
RDH
seconds, CS is driven HIGH to end the
cycle.
Similarly, in a write cycle, CS is driven LOW t
AS
seconds
after a valid address. WE is then driven low after t
ACS
seconds
for a minimum of t
WD
seconds. Valid data must be
present for a minimum of t
DS
seconds
before WE is driven
HIGH again. After a minimum of t
WDH
seconds, CS is driven
HIGH to end the cycle.
Reset
Reset timing is detailed in Figure 17. Setting the RESET pin
to LOW for a period of t
RESET
seconds forces the audio
outputs LOW and re-initializes the internal control circuitry
including returning all Host Interface Register values to their
original default values. The RESET pin can be used for
synchronizing multiple devices.
Non-Standard Sample Distributions
Gennum Corporation has made every effort to maximize
compatibility of the GS9023 with other Embedded Audio
data
streams.
Unfortunately,
implementations (i.e. non-standard sample distributions)
Gennum cannot guarantee compatibility with all Embedded
Audio data streams.
due
to
variations
in
Interconnection with GS9032 or GS7005
The user should pay special attention when laying out the
GS9023 to operate with the GS9032 or GS7005. The MSB
to LSB convention is consistent between the GS9023 and
GS9022 but reversed with respect to the GS9032 or
GS7005. Layout complexity can be minimized by placing
the GS9023 and the GS9032 or GS7005 on opposite sides
of the printed circuit board (PCB).
TABLE 13: Audio Video Delay
“
BUFSEL[1:0]
”
MODE
MULTIPLEX (us)
DEMULTIPLEX
(us)
MULTIPLEX/DEMULTIPLEX
CONNECTION (us)
0
(70 Sample)
875
541
1416
1
(26 Sample -
Default)
250
312
563
2
(20 Sample)
187
250
437
NOTE: When the video signal is in D2 format, the delay is fixed at 70 samples (1416 us).
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