參數(shù)資料
型號: GS9025
英文描述: GENLINX II Serial Digital Receiver
中文描述: GENLINX二串行數(shù)字接收機
文件頁數(shù): 17/30頁
文件大?。?/td> 445K
代理商: GS9025
19922 - 2
17
G
In the case where the input signal disappears, TRSs will
continue to be inserted based on the last detected
standard. Further, if a TRS is already in the correct location,
it will be overwritten which may have the effect of correcting
the TRS-ID word.
TRS insertion will function incorrectly if the flywheel is
disabled. Thus if the flywheel is disabled the TRS_INSERT
function should be disabled as well.
4.5 Clipping And TRS Blanking/Insertion
Asserting the CLIP_TRS pin HIGH turns on three features
described above:
ITU-R-601 Clipping,
TRS Blanking, and
TRS Insertion
These three functions can also be turned on individually
through the HOSTIF as described above. THE CLIP_TRS
pin is logically ORed with each of the three bits from the
HOSTIF table. As a result, as long as the CLIP_TRS pin is
asserted, these functions cannot be turned off via the
HOSTIF.
4.6 Ancillary Header
Updating of the ANC headers can occur to facilitate 8-bit to
10-bit conversion. If the ANC_HEADER bit of the HOSTIF
write table is set HIGH, all 3FC-3FF data values
corresponding to component ANC headers are remapped
to 3FF in the output data stream.
For example, if 8 bit data is input to the device, the ANC
header of 00, FF, FF will appear as 000, 3FC, 3FC and will
be remapped to 000, 3FF, 3FF by the GS9020A.
5.0 HOST INTERFACE TABLES
The HOST INTERFACE TABLES (HOSTIF) refer to memory
locations within the GS9020A which store functional
information about the device. There are two tables, a write
table and read table.
The write table is organized into 15 word locations (each 8
bits wide) as shown in Table 2 and is used to set various
configuration/flag bits. The read table is organized into 23
word locations (each 8 bits wide) as shown in Table 3 and is
used to read status information from the device.
The HOSTIF tables can be accessed via an I
2
C (Inter-
Integrated Circuit) serial interface or an 8-bit parallel
interface. The HOSTIF_MODE pin selects which interface is
used. If the HOSTIF_MODE pin is HIGH, the HOSTIF
operates in I
2
C mode. If the HOSTIF_MODE pin is LOW, the
HOSTIF operates in parallel mode.
Note that many bits stored in the tables are also available
as device pins. Bits in the write table that have a default
value of 0 are logically ORed with the corresponding pin.
Write table control bits VBLANKS/L and BLANK_EN, which
have a default value of 1, are logically ANDed with the
corresponding pin. However, write table control bit
ANC_CHKSM, which has a default value of 1, is logically
ORed with the corresponding pin. Therefore, to use the
ANC_CHKSM pin, the ANC_CHKSM control bit must first be
set to 0.
If the HOST interface is not going to be used, the best way
to set the related pins is as follows:
HOSTIF_MODE = LOW
CS = HIGH
R/W = HIGH
A/D = DON'T CARE (BUT NOT FLOATING)
P[7:0] = N/C
PIN
LOGIC OPR
HOST BIT
TRS_INSERT
PIN
LOGIC OPR
HOST BIT
CLIP_TRS
OR
601_CLIP
TRS_BLANK
TRS_INSERT
PIN
LOGIC OPR
HOST BIT
ANC_HEADER
PIN
LOGIC OPR
HOST BIT
HOSTIF_MODE
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