19922 - 2
4
G
PIN CONNECTIONS
PIN DESCRIPTIONS
NUMBER
SYMBOL
TYPE
DESCRIPTION
6, 7
SDI, SDI
I
Differential serial data inputs.
10, 11
SCI, SCI
I
Differential serial clock inputs.
15
HOSTIF_MODE
I
Host interface mode select. When HIGH, the host interface is configured for I
2
C mode. When
LOW, the host interface is configured for parallel port mode.
16
FIFOE/S
I
FIFO_RESET pulse control. When HIGH, the output FIFO_RESET pulse occurs on the EAV
word. When LOW, the output FIFO_RESET pulse occurs on the SAV word.
17
CRC_MODE
I
CRC_MODE enable. When HIGH, CRC_MODE is enabled. When LOW, CRC_MODE is
disabled.
18 - 20
P[7:5]
I/O
In parallel port mode, these are bits 7:5 of the host interface address/data bus. In I
2
C mode,
these pins must be set LOW.
21
SCL/P4
I/O
In parallel port mode, this is bit 4 of the host interface address/data bus. In I
2
C mode, this is the
serial clock input for the I
2
C port.
22
SDA/P3
I/O
In parallel port mode, this is bit 3 of the host interface address/data bus. In I
2
C mode, this is the
serial data pin for the I
2
C port.
23 - 25
A[2:0]/P[2:0]
I/O
In parallel port mode, these are bits 2:0 of the host interface address/data bus. In I
2
C mode,
these are input bits which define the I
2
C slave address for the device.
26
R/W
I
Parallel port read/write control. When HIGH, the parallel port is configured as an output (read
mode). When LOW, the parallel port is configured as an input (write mode). In I
2
C mode, this
pin must be set HIGH.
VDD
GND
GND
VDD
VDD
SDI
SDI
SDI
VDD
SDI
VDD
SCI
SCI
SCI
VDD
SCI
VDD
GND
HOSTIF_MODE
FIFOE/S
CRC_MODE
P7
P6
P5
DOUT9
DOUT8
DOUT7
DOUT6
DOUT5
DOUT4
DOUT3
DOUT2
DOUT1
VDD
GND
DOUT0
PCLKOUT
FIFO_RESET
NO_EDH
FLYWDIS
INTERRUPT
F_R/W
S0
S1
A
T
C
A
B
S
B
V
S
S
S
S
V
G
F
F
F
F
H
V
S
S
A
A
A
R
A
C
V
G
R
S
S
S
S
F
F
F
F
F
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
GS9020A
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