參數(shù)資料
型號(hào): GT28F320D18B120
英文描述: x16 Flash EEPROM
中文描述: x16閃存EEPROM
文件頁(yè)數(shù): 8/83頁(yè)
文件大?。?/td> 836K
代理商: GT28F320D18B120
28F320D18
4
Product Preview
NOTE:
Flash upgrade address lines are shown for A
21
(64-Mbit flash) and A
22
(128-Mbit flash) for information
purposes only since these devices are currently not available. Lower density devices will not have the
upper address solder balls. Routing is not recommended in this area.
2.3
Memory Blocking Organization
The device is divided into two physical partitions. This allows it to perform simultaneous read-
while-write and read-while-erase operations. The device’s asymmetrically blocked architecture
enables system code and data integration within a single flash device. Each block can be erased
independently. See
Figure 2, “32-Mbit Top Parameter Memory Map” on page 6
and and
Figure 3,
“32-Mbit Bottom Parameter Memory Map” on page 7
for block address locations.
Figure 1.
60-Ball μBGA* Package Ballout
A
B
C
D
E
F
G
A
11
A
8
v
SS
v
CC
v
PP
A
18
A
6
A
4
DU
DU
DU
DU
A
12
A
9
A
20
CLK
RST#
A
17
A
5
A
3
A
13
A
10
ADV#
WE#
A
19
A
7
A
2
A
15
A
14
WAIT#
A
16
D
12
WP#
A
1
V
CCQ
D
15
D
6
D
4
D
2
D
1
CE#
A
0
V
SS
D
14
D
13
D
11
D
10
D
9
D
0
OE#
D
7
V
SSQ
D
5
v
CC
D
3
V
CCQ
D
8
V
SSQ
A
4
A
6
A
18
v
PP
v
CC
V
SS
A
8
A
11
DU
DU
DU
DU
A
3
A
5
A
17
RST#
CLK
A
20
A
9
A
12
A
2
A
7
WE#
ADV#
A
19
A
10
A
13
A
1
A
14
WP#
D
12
A
16
WAIT#
A
15
A
0
CE#
D
1
D
2
D
4
D
6
D
15
V
CCQ
OE#
D
0
D
9
D
10
D
11
D
13
D
14
V
SS
V
SSQ
D
8
V
CCQ
D
3
V
CC
D
5
V
SSQ
D
7
A
B
C
D
E
F
G
Top View - Ball Side Down
Complete Ink Mark Not Shown
Bottom View - Ball Side Up
8
7
6
5
4
3
2
1
1
2
3
4
5
6
7
8
A
21
A
22
A
22
A
21
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