Rev. 5.0, 09/04, page ix of xviii
7.1.4
7.1.5
Register Descriptions (1) (Short Address Mode)..............................................................200
7.2.1
Memory Address Registers (MAR).....................................................................200
7.2.2
I/O Address Registers (IOAR).............................................................................201
7.2.3
Execute Transfer Count Registers (ETCR)..........................................................201
7.2.4
Data Transfer Control Registers (DTCR)............................................................203
Register Descriptions (2) (Full Address Mode)................................................................206
7.3.1
Memory Address Registers (MAR).....................................................................206
7.3.2
I/O Address Registers (IOAR).............................................................................206
7.3.3
Execute Transfer Count Registers (ETCR)..........................................................207
7.3.4
Data Transfer Control Registers (DTCR)............................................................209
Operation ..........................................................................................................................215
7.4.1
Overview..............................................................................................................215
7.4.2
I/O Mode..............................................................................................................217
7.4.3
Idle Mode.............................................................................................................219
7.4.4
Repeat Mode........................................................................................................222
7.4.5
Normal Mode.......................................................................................................225
7.4.6
Block Transfer Mode...........................................................................................228
7.4.7
DMAC Activation................................................................................................233
7.4.8
DMAC Bus Cycle................................................................................................235
7.4.9
Multiple-Channel Operation................................................................................241
7.4.10 External Bus Requests, DRAM Interface, and DMAC........................................242
7.4.11 NMI Interrupts and DMAC .................................................................................243
7.4.12 Aborting a DMAC Transfer.................................................................................244
7.4.13 Exiting Full Address Mode..................................................................................245
7.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode..........................246
Interrupts...........................................................................................................................247
Usage Notes......................................................................................................................248
7.6.1
Note on Word Data Transfer................................................................................248
7.6.2
DMAC Self-Access..............................................................................................248
7.6.3
Longword Access to Memory Address Registers................................................248
7.6.4
Note on Full Address Mode Setup.......................................................................248
7.6.5
Note on Activating DMAC by Internal Interrupts...............................................249
7.6.6
NMI Interrupts and Block Transfer Mode...........................................................250
7.6.7
Memory and I/O Address Register Values ..........................................................250
7.6.8
Bus Cycle when Transfer is Aborted...................................................................251
7.6.9
Transfer Requests by A/D Converter...................................................................251
Input/Output Pins.................................................................................................198
Register Configuration.........................................................................................198
7.2
7.3
7.4
7.5
7.6
Section 8 I/O Ports.............................................................................................253
8.1
Overview...........................................................................................................................253
8.2
Port 1.................................................................................................................................256
8.2.1
Overview..............................................................................................................256