Rev. 5.0, 09/04, page xi of xviii
9.2.5
9.2.6
9.2.7
9.2.8
9.2.9
9.2.10 Timer I/O Control Register (TIOR).....................................................................335
9.2.11 Timer Output Level Setting Register C (TOLR) .................................................337
CPU Interface....................................................................................................................339
9.3.1
16-Bit Accessible Registers.................................................................................339
9.3.2
8-Bit Accessible Registers...................................................................................341
Operation ..........................................................................................................................342
9.4.1
Overview..............................................................................................................342
9.4.2
Basic Functions....................................................................................................342
9.4.3
Synchronization...................................................................................................350
9.4.4
PWM Mode..........................................................................................................352
9.4.5
Phase Counting Mode..........................................................................................356
9.4.6
16-Bit Timer Output Timing................................................................................358
Interrupts...........................................................................................................................359
9.5.1
Setting of Status Flags .........................................................................................359
9.5.2
Timing of Clearing of Status Flags......................................................................361
9.5.3
Interrupt Sources..................................................................................................362
Usage Notes......................................................................................................................363
Timer Interrupt Status Register B (TISRB).........................................................326
Timer Interrupt Status Register C (TISRC).........................................................329
Timer Counters (16TCNT)..................................................................................331
General Registers (GRA, GRB)...........................................................................332
Timer Control Registers (16TCR) .......................................................................333
9.3
9.4
9.5
9.6
Section 10 8-Bit Timers.....................................................................................375
10.1
Overview...........................................................................................................................375
10.1.1 Features................................................................................................................375
10.1.2 Block Diagram.....................................................................................................377
10.1.3 Pin Configuration.................................................................................................378
10.1.4 Register Configuration.........................................................................................379
10.2
Register Descriptions........................................................................................................380
10.2.1 Timer Counters (8TCNT)....................................................................................380
10.2.2 Time Constant Registers A (TCORA).................................................................381
10.2.3 Time Constant Registers B (TCORB)..................................................................382
10.2.4 Timer Control Register (8TCR)...........................................................................383
10.2.5 Timer Control/Status Registers (8TCSR) ............................................................386
10.3
CPU Interface....................................................................................................................391
10.4
Operation ..........................................................................................................................393
10.4.1 8TCNT Count Timing..........................................................................................393
10.4.2 Compare Match Timing.......................................................................................394
10.4.3 Input Capture Signal Timing ...............................................................................395
10.4.4 Timing of Status Flag Setting..............................................................................396
10.4.5 Operation with Cascaded Connection..................................................................397