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參數(shù)資料
| 型號(hào)： | HA12240FP |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | 150000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 總線接口驅(qū)動(dòng)器/接收器IC |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 163K |
| 代理商： | HA12240FP |
HA12240FP
Rev.1.0, Dec.01.2003, page 5 of 23
Electrical Characteristics
(cont.)
(V
CC
= 5.0 V, Ta = 25°C)
Test
Pin
Item
Symbol
Min
Typ
Max
Unit
Test Conditions
Test
Circuit
Power-supply off output leakage
current
Standby mode current drain
I
OLEAK
—
—
1
μ
A
V
CC
= 0 V, V8 = 0 V, V6 = 5 V,
V1 = 0 V, V3 = 0 V, SW1 ON
V1 = 5 V, V3 = 0 V, V8 = 0 V
6
Fig. 4
I
CCstb
Istb-Leak
—
—
1
μ
A
μ
A
7
Fig. 4
Standby mode output leakage
current
Standby mode high-level input
voltage
—
—
1
V1 = 5 V, V3 = 0 V, V8 = 0 V,
V6 = 5 V, SW1 ON
V8 = 0
→
5 V, V8 when pin5,6 = 2.3
V or more, V1 = 0 V, V3 = 0 V
V8 = 5
→
0 V, V8 when current
flowing into pin7 = 1
μ
A or less,
V1 = 5 V, V3 = 0 V
V1 = 5 V, V3 = 0 V, V8 = 5 V
6
Fig. 4
VstbH
2
—
—
V
8
Fig. 1
Standby mode low-level input
voltage
VstbL
—
—
0.9
V
8
Fig. 1
Standby mode high-level input
current
IstbH
—
50
100
μ
A
8
Fig. 1
Standby mode low-level input
current
IstbL
—
—
1
μ
A
V1 = 5 V, V3 = 0 V, V8 = 0 V
8
Fig. 1
V
CC
0 V
V
CC
×
0.1
V
CC
×
0.9
0 V
30 mV
f = 50 kHz
Duty = 50%
110 mV
BUS(+) – BUS(–)
R (pin 2)
Input waveform
0 V
V
CC
×
0.1
V
CC
×
0.9
T
TR1
T
TR2
T
DLY1
T
DLY2
Input/Output Waveform Figure
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