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參數(shù)資料
| 型號： | HA16163T |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | Synchronous Phase Shift Full-Bridge Control IC |
| 中文描述： | 同步移相全橋控制IC |
| 文件頁數(shù)： | 12/30頁 |
| 文件大?。?/td> | 294K |
| 代理商： | HA16163T |
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HA16163T
Rev.5.0, Mar.15.2004, page 12 of 29
The remote on and off threshold voltages are provided with hysteresis of 84 mV (typ). Remote control can be
performed by means of analog input as shown in the diagram below as well as by means of logic control. The
following diagram shows an example in which the power supply set input voltage is sensed by means of the REMOTE
pin, and the power supply set start-up voltage is set to 34 V, and the shutdown voltage to 32 V.
GND
HA16163
10k
10k
220k
R2
R1
5V(VREF)
VIN(on) = VON(remote)
×
(R1+R2)/R2
= 1.417V
×
24
= 34.008V
VIN(off) = VOFF(remote)
×
(R1+R2)/R2
= 1.333V
×
24
= 31.992V
Remote control circuit
(logic input)
VIN sense circuit
(analog input)
100p
REMOTE
Power Stage
Full-bridge
control
VIN
Figure 3
Start-up Counter
When the VREF
GOOD
signal (internal signal) goes to the logic low level, the HA16163 starts operating as a controller.
The VREF
GOOD
signal is created from the REMOTE comparator and VREFGOOD circuit output via a 32-clock start-
up counter.
+
5V
Generator
Start-up
counter
32 clock
ON: 1.417V
OFF: 1.333V
REMOTE
VCC
UVL
L
UVLO
H
L
H
VREF
GOOD
VREF
VREF
GOOD
From Oscillator
Circuit Bias
Figure 4
Therefore, the start of IC operation is a 32-count later than UVLO release or the remote on trigger. When the oscillator
frequency is set to 1 MHz, this represents a delay of 32
μ
s. This delay enables operation to be halted until VREF (5 V)
stabilizes when UVLO is released. Note that the start-up counter operates when VREF rises or when a remote on
operation is performed, but does not operate when VREF falls or when a remote off operation is performed (there is no
logic delay due to the start-up counter).
9.8V
7.9V
4.4V
4.6V
32 counts
Start of
operation
Operation
halted
VCC
VREF
VREF
GOOD
(Internal signal)
RES
(Internal signal)
Figure 5
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