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參數(shù)資料
| 型號： | HA16163T |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | Synchronous Phase Shift Full-Bridge Control IC |
| 中文描述： | 同步移相全橋控制IC |
| 文件頁數(shù)： | 6/30頁 |
| 文件大小： | 294K |
| 代理商： | HA16163T |
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HA16163T
Rev.5.0, Mar.15.2004, page 6 of 29
Electrical Characteristics
(cont.)
(Ta = 25°C, Vcc = 12 V, RT = 33 k
, Rdelay = 51 k
, unless otherwise specified.)
Symbol
Min
Typ
Max
V
RAMP
—
0.4 *
1
—
I
RAMP
–5
–0.8
5
I
SINK-RAMP
8
26
—
Dmin
—
0 *
1
*
4
—
Dmax
—
97.0 *
1
*
4
—
Tpd
—
30
60
T
D1, 2, 3
22
33.5
45
V
D1, 2, 3
1.9
2.0
2.1
I
SS
–14
–10
–6
I
RES-SS
5
10
—
V
RES-SS
0.25
0.40
0.55
V
OH-SS
3.9
4.0
4.1
Notes: 1. Reference values for design. Not 100% tested in production.
2. Tpd is defined as;
Item
Phase
modulator
RAMP offset voltage
RAMP bias current
RAMP sink current
Minimum phase shift
Maximum phase shift
Delay to OUT-C, -D *
2
DELAY-1, -2, -3 *
3
Terminal voltage
Source current
Discharge current
Soft-start reset voltage
SS high voltage
Unit
V
μ
A
mA
%
%
ns
ns
V
μ
A
mA
V
V
Test Conditions
RAMP = 0.3V
RAMP = 1V, COMP = 0V
RAMP = 1V, COMP = 0V
RAMP = 0V, COMP = 2.1V
COMP = 2.1V
Delay set R = 51k
Delay set R = 51k
SS = 1V
SS = 1V, REMOTE = 0V
Measured on SS
Delay
Soft start
RAMP
1V
0V
50%
50%
Tpd
5V
0V
OUT-C/D
3. T
D1, 2, 3
are defined as;
T
D2
T
D1
T
D1
T
D2
50%
OUT-A
For primary
control
For secondary
control
OUT-B
OUT-C
OUT-D
OUT-E
T
D3
T
D3
OUT-F
4. Maximum/Minimum phase shift is defined as;
D =
×
2
×
100 (%)
T
2
T
1
T
2
T
1
OUT-A
OUT-D
T
2
T
1
OUT-B
OUT-C
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