參數(shù)資料
型號: HB56U432SB-5N
元件分類: DRAM
英文描述: 4M X 32 EDO DRAM MODULE, 50 ns, SMA72
封裝: SIP-72
文件頁數(shù): 24/25頁
文件大?。?/td> 277K
代理商: HB56U432SB-5N
HB56U832 Series, HB56U432 Series
8
DC Characteristics (Ta = 0 to 70
°C, V
CC = 5 V ± 5%, VSS = 0 V) (HB56U832)
50 ns
60 ns
70 ns
Parameter
Symbol Min
Max Min
Max Unit
Test conditions
Notes
Operating current
I
CC1
840
760
680
mA
t
RC = min
1, 2
Standby current
I
CC2
32
32
32
mA
TTL interface,
RAS, CAS = V
IH,
Dout = High-Z
16
16
16
mA
CMOS interface,
RAS, CAS
≥ V
CC – 0.2
V,
Dout = High-Z
Standby current
(L-version)
I
CC2
2.4
2.4
2.4
mA
CMOS interface,
RAS, CAS
≥ V
CC – 0.2
V, Dout = High-Z
RAS-only refresh
current
I
CC3
840
760
680
mA
t
RC = min
2
Standby current
I
CC5
—80
80
—80
mA
RAS = V
IH, CAS = VIL,
Dout = enable
1
CAS-before-RAS
refresh current
I
CC6
840
760
680
mA
t
RC = min
EDO page mode
current
I
CC7
760
680
640
mA
t
HPC = min
1, 3
Battery backup current
(Standby with CBR
refresh) (L-version)
I
CC10
5.6
5.6
5.6
mA
CMOS interface,
Dout = High-Z,
CBR refresh:
t
RC = 62.5 s,
t
RAS ≤ 0.3 s
Input leakage current
I
LI
–10
10
–10
10
–10
10
A
0 V
≤ Vin ≤ 5.5 V
Output leakage current I
LO
–10
10
–10
10
–10
10
A
0 V
≤ Vout ≤ 5.5 V,
Dout = disable
Output high voltage
V
OH
2.4
V
CC
2.4
V
CC
2.4
V
CC
V
High Iout = –2 mA
Output low voltage
V
OL
0
0.4
0
0.4
0
0.4
V
Low Iout = 2 mA
Notes: 1. I
CC depends on output load condition when the device is selected, ICC max is specified at the
output open condition.
2. Address can be changed once or less while
RAS = V
IL.
3. Address can be changed once or less while
CAS = V
IH.
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