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參數(shù)資料
| 型號： | HB56U432SB-5N |
| 元件分類： | DRAM |
| 英文描述： | 4M X 32 EDO DRAM MODULE, 50 ns, SMA72 |
| 封裝： | SIP-72 |
| 文件頁數(shù)： | 6/25頁 |
| 文件大小： | 277K |
| 代理商： | HB56U432SB-5N |
HB56U832 Series, HB56U432 Series
14
Notes: 1. AC measurements assume t
T = 2 ns.
2. An initial pause of 200
s is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing
RAS-only refresh cycle or CAS-before-RAS
refresh). If the internal refresh counter is used, a minimum of eight
CAS-before-RAS refresh
cycles are required.
3. Operation with the t
RCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a
reference point only; if t
RCD ≥ tRCD (max) + tAA (max) - tCAC (max), then access time is controlled
exclusively by t
CAC.
4. Operation with the t
RAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a
reference point only; if t
RAD is greater than the specified tRAD (max) limit, then access time is
controlled exclusively by t
AA.
5. V
IH (min) and VIL (max) are reference levels for measuring timing of input signals.
Also, transition
times are measured between V
IH (min) and VIL (max).
6. Assumes that t
RCD ≤ tRCD (max) and tRAD ≤ tRAD (max).
If t
RCD or tRAD is greater than the maximum
recommended value shown in this table, t
RAC exceeds the value shown.
7. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
8. Assumes that t
RCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max).
9. Assumes that t
RAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max).
10. Either t
RCH or tRRH must be satisfied for a read cycles.
11. t
OFF (max) defines the time at which the outputs achieve the open circuit condition and are not
referred to output voltage levels.
12. Early write cycle only (t
WCS ≥ tWCS (min)).
13. These parameters are referred to
CAS leading edge in early write cycles.
14. t
RASP defines RAS pulse width in EDO page mode cycles.
15. Access time is determined by the longest among t
AA, t CAC and t CPA.
16. t
HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode
read cycles.
17. When output buffers are enabled once, sustain the low impedance state until valid data is
obtained. When output buffer is turned on and off within a very short time, generally it causes
large V
CC / VSS line noise, which causes to degrade VIH min./ V IL max level.
18. All the V
CC and VSS pins shall be supplied with the same voltages.
19. Data output turns off and becomes high impedance from later rising edge of
RAS and CAS.
Hold time and turn off time are specified by the timing specifications of later rising edge of
RAS
and
CAS between t
OHR and tOH , and between tOFR and t OFF.
20. XXX: H or L (H: V
IH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied V
IH or VIL.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HB56U432SB-5NL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 EDO Page Mode DRAM Module |
| HB56U432SB-6BN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 EDO Page Mode DRAM Module |
| HB56U432SB-6N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 EDO Page Mode DRAM Module |
| HB56U432SB-6NL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 EDO Page Mode DRAM Module |
| HB56U432SB-7BN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 EDO Page Mode DRAM Module |
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