參數(shù)資料
型號(hào)： HC55130IB
廠商： INTERSIL CORP
元件分類： 模擬傳輸電路
英文描述： IC-VLTG REG +6V TO220 ISO
中文描述： TELECOM-SLIC, PDSO28
封裝： PLASTIC, MS-013-AE, SOIC-28
文件頁(yè)數(shù)： 22/35頁(yè)
文件大?。?/td> 382K
代理商： HC55130IB
4-22
Operation of Line Voltage Measurement
A few of the SLICs in the UniSLIC14 family feature Line
Voltage Measurement (LVM) capability. This feature provides
a pulse on the GKD_LVM output pin that is proportional to
the loop voltage. Knowing the loop voltage and thus the loop
length, other basic cable characteristics such as attenuation
and capacitance can be inferred. Decisions can be made
about gain switching in the CODEC to overcome line losses
and verification of the 2-wire circuit integrity.
The LVM function can only be activated in the off hook
condition in either the forward or reverse operating states.
The LVM uses the ring signal supplied to the SLIC as a
timebase generator. The loop resistance is determined by
monitoring the pulse width of the output signal on the
GKD_LVM pin. The output signal on the GKD_LVM pin is a
square wave for which the average duration of the low state
is proportional to the average voltage between the tip and
ring terminals. The loop resistance is determined by the tip
to ring voltage and the constant loop current. Reference
Figure 20.
Although the logic state changes to the Test Active State
when performing this test, the SLIC is still powered up in the
active state (forward or reverse) and the subscriber is
unaware the measurement is being taken.
Polarity Reversal
Most of the SLICs in the UniSLIC14 family feature full
polarity reversal. Full polarity reversal means that the SLIC
can: transmit, determine the status of the line (on hook and
off hook) and provide “silent” polarity reversal. The value of
RSYNC_REV resistor is limited between 34.8k (10ms) and
73.2k (21ms). Reference Equation 39 to program the polarity
reversal time.
Transhybrid Balance
If a low cost CODEC is chosen that does not have a transmit
op-amp, the UniSLIC14 family of SLICs can solve this
problem without the need for an additional op-amp. The
solution is to use the
P
rogrammable
T
ransmit
G
ain pin (PTG)
as an input for the receive signal (V
RX
). When the PTG pin is
connected to a divider network (R1 and R2 Figure 21) and the
value of R1 and R2 is much less than the internal 500k
resistors, two things happen. First the transmit gain from V
RX
to V
TX
is reduced by half. This is the result of shorting out the
bottom 500k
resistor with the much smaller external resistor.
And second, the input signal from V
RX
is also decreased in
half by resistors R1 and R2. Transhybrid balance occurs when
these two, equal but opposite in phase, signals are cancelled
at the input to the output buffer.
Loopback Tests
4-Wire Loopback Test
This feature can be very useful in the testing of line cards
during the manufacturing process and in field use. The test
is unobtrusive, allowing it to be used in live systems.
Reference Figure 22.
Most systems do not provide 4-wire loopback test
capability because of costly relays needed to switch in
external loads. All the SLICs in the UniSLIC14 family can
easily provide this function when configured in the Open
Circuit logic state. With the PTG pin floating, the signal on
the V
TX
output is 180
o
out of phase and approximately 2
times the V
RX
input signal. If the PTG pin is grounded, then
the amplitude will be approximately the same as the input
signal and 180
o
out of phase.
FIGURE 19. RINGING SEQUENCE
OFF
ON
OFF
RELAY DRIVER
RINGING CURRENT
IN LINE
SHD OUTPUT
RINGING CODE
APPLIED
RING SYNC
PULSE
RINGING VOLTAGE
(A)
(B)
(C)
FIGURE 20. OPERATION OF THE LINE VOLTAGE
MEASUREMENT CIRCUIT
TIP
RING
DT
DR
RING
GEN
GKD_LVM
RING
GEN
FREQ
PULSE WIDTH
PROPORTIONAL TO
LOOP LENGTH
P
LOOP LENGTH
W
UniSLIC14
FIGURE 21. TRANSHYBRID BALANCE USING THE PTG PIN
V
TX
V
RX
V
TX
-
+
V
RX
+
-
500K
500K
500K
PTG
R1
+
-
I
X
5
A = 1
I
X
R2
500K
UniSLIC14
HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HC55130IB96 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Power Universal SLIC Family
HC55130IBZ 功能描述:電信線路管理 IC LW PWR SLIC 63DB BALANCE RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
HC55130IBZ96 功能描述:電信線路管理 IC LW PWR SLIC 63DB BALANCE RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
HC55130IM 制造商:Rochester Electronics LLC 功能描述:LOW PWR SLIC,63DB BALANCE - Bulk 制造商:Harris Corporation 功能描述:
HC55130IMZ 功能描述:電信線路管理 IC LW PWR SLIC 63DB BALANCE RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
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