Clock Generator Module (CGM)
Acquisition/Lock Time Specifications
MC68HC908AT32
—
Rev. 2.0
General Release Specification
MOTOROLA
Clock Generator Module (CGM)
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163
L
G
R
Also important is the operating voltage potential applied to V
DDA
. The
power supply potential alters the characteristics of the PLL. A fixed value
is best. Variable supplies, such as batteries, are acceptable if they vary
within a known range at very slow speeds. Noise on the power supply is
not acceptable, because it causes small frequency errors which
continually change the acquisition time of the PLL.
Temperature and processing also can affect acquisition time because
the electrical characteristics of the PLL change. The part operates as
specified as long as these influences stay within the specified limits.
External factors, however, can cause drastic changes in the operation of
the PLL. These factors include noise injected into the PLL through the
filter capacitor, filter capacitor leakage, stray impedances on the circuit
board, and even humidity or circuit board contamination.
8.10.3 Choosing a Filter Capacitor
As described in
8.10.2 Parametric Influences on Reaction Time
, the
external filter capacitor, C
F
, is critical to the stability and reaction time of
the PLL. The PLL is also dependent on reference frequency and supply
voltage. The value of the capacitor must, therefore, be chosen with
supply potential and reference frequency in mind. For proper operation,
the external filter capacitor must be chosen according to this equation:
For acceptable values of C
fact
, see
Section 29. Electrical
Specifications
. For the value of V
DDA
, choose the voltage potential at
which the MCU is operating. If the power supply is variable, choose a
value near the middle of the range of possible supply values.
This equation does not always yield a commonly available capacitor
size, so round to the nearest available size. If the value is between two
different sizes, choose the higher value for better stability. Choosing the
lower size may seem attractive for acquisition time improvement, but the
PLL may become unstable. Also, always choose a capacitor with a tight
tolerance (
±
20% or better) and low dissipation.
C
F
C
fact
V
f
rdv
------------
=
F
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n
.