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參數(shù)資料
| 型號： | HD3-6409-9Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 14/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ENCODER-DECODER CMOS 20-PDIP |
| 標(biāo)準(zhǔn)包裝： | 180 |
| 類型： | 解碼器 |
| 應(yīng)用： | 光纖 |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 20-PDIP |
| 包裝： | 管件 |
9
FN2951.3
October 15, 2008
Capacitance TA = +25°C, Frequency = 1MHz.
SYMBOL
PARAMETER
TEST CONDITIONS
TYP
UNITS
CIN
Input Capacitance
All measurements are referenced to device GND
10
pF
COUT
Output Capacitance
12
pF
AC Electrical Specifications VCC = 5.0V ±10%, TA = -40°C to +85°C (HD-6409-9).
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 7)
MIN
MAX
UNITS
fC
Clock Frequency
-
16
MHz
tC
Clock Period
-
1/fC
-sec
t1
Bipolar Pulse Width
-
tC+10
-
ns
t3
One-Zero Overlap
-
tC-10
ns
tCH
Clock High Time
f = 16.0MHz
20
-
ns
tCL
Clock Low Time
f = 16.0MHz
20
-
ns
tCE1
Serial Data Setup Time
-
120
-
ns
tCE2
Serial Data Hold Time
-
0
-
ns
tCD2
DCLK to SDO, NVM
-
40
ns
tR2
ECLK to BZO
-
40
ns
tr
Output Rise Time (All except Clock)
-
50
ns
tf
Output Fall Time (All except Clock)
-
50
ns
tr
Clock Output Rise Time
-
11
ns
tf
Clock Output Fall Time
-
11
ns
tCE3
ECLK to BZO, BOO
Notes 8, 9
0.5
1.0
DBP
tCE4
CTS Low to BZO, BOO Enabled
Notes 8, 9
0.5
1.5
DBP
tCE5
CTS Low to ECLK Enabled
Notes 8, 9
10.5
11.5
DBP
tCE6
CTS High to ECLK Disabled
Notes 8, 9
-
1.0
DBP
tCE7
CTS High to BZO, BOO Disabled
Notes 8, 9
1.5
2.5
DBP
tCD1
UDI to SDO, NVM
Notes 8, 9
2.5
3.0
DBP
tCD3
RST Low to CDLK, SDO, NVM Low
Notes 8, 9
0.5
1.5
DBP
tCD4
RST High to DCLK, Enabled
Notes 8, 9
0.5
1.5
DBP
tR1
UDI to BZO, BOO
Notes 8, 9
0.5
1.0
DBP
tR3
UDI to SDO, NVM
Notes 8, 9
2.5
3.0
DBP
NOTES:
7. AC testing as follows: f = 4.0MHz, VIH = 70% VCC, VIL = 20% VCC, Speed Select = 16X, VOH ≥ VCC/2, VOL ≤ VCC/2, VCC = 4.5V and 5.5V.
Input rise and fall times driven at 1ns/V, Output load = 50pF.
8. Limits established by characterization and are not production tested.
9. DBP-Data Bit Period, Clock Rate = 16X, one DBP = 16 Clock Cycles; Clock Rate = 32X, one DBP = 32 Clock Cycles.
HD-6409
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