參數(shù)資料
型號： HD404448
廠商： Hitachi,Ltd.
英文描述： 4-bit HMCS400-Series microcomputer(4位單片微計算機)
中文描述： 4位HMCS400系列微機（4位單片微計算機）
文件頁數(shù)： 45/123頁
文件大?。?/td> 726K
代理商： HD404448
HD404449 Series
45
I/O Pin Type
Circuit
Pins
SI
1
, SI
2
,
INT
1
,
INT
2
, INT
3
,
EVNB
, EVND
Input pins
V
CC
Input data
SI
1
, SI
2
,,
INT
1
, etc
HLT
MIS3
PDR
Input data
INT
,
STOPC
0
INT
0
,
STOPC
Notes: 1. The MCU is reset in stop mode, and peripheral function selection is cancelled. The
HLT
signal
becomes low, and input/output pins enter high-impedance state.
2. The
HLT
signal is 1 in watch and subactive modes.
D Port (D
0
–D
13
):
Consist of 12 input/output pins and 2 input pins addressed by one bit. D
0
–D
11
are high-
current I/O pins, and D
12
and D
13
are input-only pins.
Pins D
0
–D
11
are set by the SED and SEDD instructions, and reset by the RED and REDD instructions.
Output data is stored in the port data register (PDR) for each pin. All pins D
0
–D
13
are tested by the TD and
TDD instructions.
The on/off statuses of the output buffers are controlled by D-port data control registers (DCD0–DCD2:
$02C–$02E) that are mapped to memory addresses (figure 29).
Pins D
12
and D
13
are multiplexed with peripheral function pins
STOPC
and
I NT
0
, respectively. The
peripheral function modes of these pins are selected by bits 2 and 3 (PMRC2, PMRC3) of port mode
register C (PMRC: $025) (figure 30).
R Ports (R0
0
–RC
3
):
52 input/output pins addressed in 4-bit units. Data is input to these ports by the LAR
and LBR instructions, and output from them by the LRA and LRB instructions. Output data is stored in the
port data register (PDR) for each pin. The on/off statuses of the output buffers of the R ports are controlled
by R-port data control registers (DCR0–DCRC: $030–$03C) that are mapped to memory addresses (figure
29).
Pins R0
0
–R0
2
are multiplexed with peripheral pins
I NT
1
–INT
3
, respectively. The peripheral function modes
of these pins are selected by bits 0–2 (PMRB0–PMRB2) of port mode register B (PMRB: $024) (figure
31).
Pins R3
0
–R3
2
are multiplexed with peripheral pins TOB, TOC, and TOD, respectively. The peripheral
function modes of these pins are selected by bits 0 and 1 (TMB20, TMB21) of timer mode register B2
(TMB2: $013), bits 0–2 (TMC20–TMC22) of timer mode register C2 (TMC2: $014), and bits 0–3
(TMD20–TMD23) of timer mode register D2 (TMD2: $015) (figures 32, 33, and 34).
Pins R3
3
and R4
0
are multiplexed with peripheral pins
EVNB
and EVND, respectively. The peripheral
function modes of these pins are selected by bits 0 and 1 (PMRC0, PMRC1) of port mode register C
(PMRC: $025) (figure 30).
Pins R4
1
–R4
3
are multiplexed with peripheral pins
SCK
1
, SI
1
, and SO
1
, respectively. The peripheral
function modes of these pins are selected by bit 3 (SM1A3) of serial mode register 1A (SM1A: $005), and
bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004), as shown in figures 35 and 36.
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