參數(shù)資料
型號： HD4702
廠商： Intersil Corporation
英文描述： CMOS Programmable Bit Rate Generator
中文描述： CMOS可編程比特率發(fā)生器
文件頁數(shù)： 4/8頁
文件大小： 80K
代理商： HD4702
4
Supply Current
(Static)
I
CC
ECP = V
CC
, CP = 0V,
V
CC
= 5.5V
All Other Inputs = GND,
(Note 5)
1, 2, 3
-55
≤
T
A
≤
125
-
1500
μ
A
ECP = V
CC
, CP = 0V,
V
CC
= 5.5V
All Other Inputs = V
CC
(Note 5)
1, 2, 3
-55
≤
T
A
≤
125
-
1000
μ
A
NOTES:
4. Interchanging of force and sense conditions is permitted.
5. Input Current and Quiescent Power Supply Current are relatively higher for this device because of active pull-up circuits on all inputs
except I
X
.
TABLE 2. AC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested.
AC PARAMETER
SYMBOL
CONDITIONS
GROUP A
SUBGROUPS
TEMPERATURE
(
o
C)
MIN
MAX
UNITS
Propagation Delay, I
X
to C
O
t
PLH
V
CC
= 4.5V
C
L
≤
7pF on OX
C
L
= 50pF
(Note 6)
9, 10, 11
-55
≤
T
A
≤
125
-
350
ns
Propagation Delay, I
X
to C
O
t
PHL
9, 10, 11
-55
≤
T
A
≤
125
-
275
ns
Propagation Delay, C
P
to C
O
t
PLH
9, 10, 11
-55
≤
T
A
≤
125
-
260
ns
Propagation Delay, C
P
to C
O
t
PHL
9, 10, 11
-55
≤
T
A
≤
125
-
220
ns
Propagation Delay, C
O
to Q
n
Propagation Delay, C
O
to Q
n
t
PLH
9, 10, 11
-55
≤
T
A
≤
125
-
(Note 7)
ns
t
PHL
9, 10, 11
-55
≤
T
A
≤
125
-
(Note 7)
ns
Propagation Delay, C
O
to Z
t
PLH
9, 10, 11
-55
≤
T
A
≤
125
-
85
ns
Propagation Delay, C
O
to Z
t
PHL
9, 10, 11
-55
≤
T
A
≤
125
-
75
ns
Output Transition Time (Except O
X
)
t
TLH
9, 10, 11
-55
≤
T
A
≤
125
160
ns
Output Transition Time (Except O
X
)
t
THL
9, 10, 11
-55
≤
T
A
≤
125
-
75
ns
Set-UpTime Select to C
O
t
S
9, 10, 11
-55
≤
T
A
≤
125
350
-
ns
Hold Time, Select to C
O
t
H
9, 10, 11
-55
≤
T
A
≤
125
0
-
ns
Set-UpTime, I
M
to C
O
t
S
9, 10, 11
-55
≤
T
A
≤
125
350
-
ns
Hold Time, I
M
to C
O
t
H
9, 10, 11
-55
≤
T
A
≤
125
0
-
ns
Minimum Clock Pulse Width, Low
(Notes 8, 9)
t
WCP(L)
9, 10, 11
-55
≤
T
A
≤
125
120
ns
Minimum Clock Pulse Width, High
(Notes 8, 9)
t
WCP(H)
9, 10, 11
-55
≤
T
A
≤
125
120
-
ns
Minimum I
X
Pulse Width, Low (Note 9)
t
WCP(L)
9, 10, 11
-55
≤
T
A
≤
125
160
-
ns
Minimum I
X
Pulse Width, High (Note 9)
t
WCP(H)
9, 10, 11
-55
≤
T
A
≤
125
160
-
ns
NOTES:
6. Propagation Delays (t
PLH
and t
PHL
) and Output Transition Times (t
TLH
and t
THL
) will change with Output Load Capacitance (C
L
).
Set-Up Times (t
S
), Hold Times (t
H
), and Minimum Pulse Widths (t
W
) do not vary with load capacitance.
7. For multichannel operation, Propagation Delay (C
O
to Q
n
), plus Set-Up Time, Select to C
O
, is guaranteed to be
≤
367ns.
8. The first High Level Clock Pulse alter E
CP
goes Low must be at least 350ns long to guarantee reset of all Counters.
9. It is recommended that input rise and fall times to the clock inputs (C
P
, I
X
) be less than 15ns.
TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
Device Guaranteed and 100% Tested
DC PARAMETER
SYMBOL
CONDITIONS
GROUP A
SUB-
GROUPS
TEMPERATURE
(
o
C)
MIN
MAX
UNITS
HD-4702/883
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