參數(shù)資料
型號(hào): HD4702
廠商: Intersil Corporation
英文描述: CMOS Programmable Bit Rate Generator
中文描述: CMOS可編程比特率發(fā)生器
文件頁(yè)數(shù): 5/8頁(yè)
文件大?。?/td> 80K
代理商: HD4702
5
TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS
AC PARAMETER
SYMBOL
CONDITIONS
NOTES TEMPERATURE (
o
C)
MIN
MAX
UNITS
Input Capacitance
C
IN
All Measurements
are referenced to
device ground,
f = 1MHz.
10
T
A
= 25
-
7.0
pF
Output Capacitance
C
O
10
T
A
= 25
-
15.0
pF
Propagation Delay I
X
to C
O
t
PLH
V
CC
= 4.5V
C
L
7pF on O
X
C
L
= 15pF
10, 12
-55
T
A
125
-
300
ns
Propagation Delay I
X
to C
O
t
PHL
10, 12
-55
T
A
125
-
250
ns
Propagation Delay C
P
to C
O
t
PLH
10, 12
-55
T
A
125
-
215
ns
Propagation Delay C
P
to C
O
t
PHL
10, 12
-55
T
A
125
-
195
ns
Propagation Delay C
O
to Q
n
t
PLH
10, 12
-55
T
A
125
-
(Note 11)
ns
Propagation Delay C
O
to Q
n
t
PHL
10, 12
-55
T
A
125
-
(Note 11)
ns
Propagation Delay C
O
to Z
t
PLH
10, 12
-55
T
A
125
-
75
ns
Propagation Delay C
O
to Z
t
PHL
10, 12
-55
T
A
125
-
65
ns
Output Transition Time (Except O
X
)
t
TLH
10, 12
-55
T
A
125
-
80
ns
Output Transition Time (Except O
X
)
t
THL
10, 12
-55
T
A
125
-
40
ns
NOTES:
10. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are
characterized upon initial design and after major process and/or design changes.
11. For multichannel operation, Propagation Delay (C
O
to Qn) plus Set-Up Time, Select to C
O
, is guaranteed to be
367ns.
12. Propagation Delays (t
PLH
and t
PHL
) and Output Transition Times (t
TLH
and t
THL
) will change with Output Load Capacitance (C
L
).
Set-Up Times (t
S
), Hold Times (t
H
), and Minimum Pulse Widths (t
W
) do not vary with load capacitance.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
METHOD
SUBGROUPS
Initial Test
100%/5004
-
Interim Test
100%/5004
1, 7, 9
PDA
100%
1
Final Test
100%
2, 3, 8A, 8B, 10, 11
Group A
-
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Groups C and D
Samples/5005
1, 7, 9
HD-4702/883
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