參數(shù)資料
型號(hào): HD49335HF
廠商: Renesas Technology Corp.
英文描述: CDS/PGA AND 10-bit A/D TG Converter
中文描述: 的CDS / PGA和10位A / D轉(zhuǎn)換器熱
文件頁數(shù): 17/30頁
文件大?。?/td> 323K
代理商: HD49335HF
HD49335F/HF
Rev.1.0, Feb.25.2004, page 17 of 29
Serial Interface Specifications
Timing Specifications
SDATA
STD2(Upper data)
STD1(Lower data)
address(address)
SCK
CS
f
SCK
D9
D8
D11
D10
D13
D12
D15
D14
D1
D0
D3
D2
D5
D4
D7
D6
D0
D2
D1
D4
D3
D6
D5
D7
t
INT1
t
INT2
t
su
t
ho
Latches SDATA
at SCK rising edge
Data is determined
at CS rising edge
Figure 8 Serial Interface Timing Specifications
Item
f
SCK
t
INT1,2
t
su
t
ho
Min
50 ns
50 ns
50 ns
Max
5 MHz
Notes: 1. 3 byte continuous communications.
2. Input SCK with 24 clock when CS is Low.
3. It becomes invalid when data communications are stopped on the way.
4. Data becomes a default with hardware reset.
5. Input more than double frequency of SCK to the CLK_in when transfer
the serial data.
The Kind of Data
Data address has 256 type. H’00 to H’FF
H’00
:
:
H’EF
H’F0
:
:
H’FF
Address map of each data referred to other sheet.
Details of timing generator refer to the timing chart on the other sheet together with this specification.
This specification only explains about the data of CDS part.
Data at timing generator part
Data at CDS part
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HD49335HNP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:CDS/PGA & 10-bit A/D TG Converter
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