Figure
Figure 1-1
Figure 1-2
Figure 1-3
Figure 1-4
Block Diagram......................................................................................................
Pin Arrangement (FP-80A, Top View) .................................................................
Pin Arrangement (CP-84, Top View)....................................................................
Pin Arrangement (CG-84, Top View)...................................................................
2
6
7
8
Figure 2-1
Address Space Map............................................................................................... 20
Figure 3-1
Figure 3-2
Figure 3-3
Figure 3-4
Figure 3-5
Figure 3-6
Figure 3-7
Figure 3-8
Figure 3-9
Figure 3-10
Figure 3-11
Figure 3-12
Figure 3-13
Figure 3-14
Figure 3-15
Figure 3-16
Figure 3-17(a) External Device Access Timing (read) ................................................................. 56
Figure 3-17(b) External Device Access Timing (write)................................................................ 57
CPU Registers....................................................................................................... 26
Stack Pointer ......................................................................................................... 27
Register Data Formats........................................................................................... 32
Memory Data Formats .......................................................................................... 33
Data Transfer Instruction Codes............................................................................ 37
Arithmetic, Logic, and Shift Instruction Codes.................................................... 40
Bit Manipulation Instruction Codes...................................................................... 46
Branching Instruction Codes................................................................................. 48
System Control Instruction Codes......................................................................... 50
Block Data Transfer Instruction/EEPROM Write Operation Code...................... 51
Operating States.................................................................................................... 51
State Transitions.................................................................................................... 52
On-Chip Memory Access Cycle ........................................................................... 54
Pin States during On-Chip Memory Access Cycle............................................... 54
On-Chip Register Field Access Cycle................................................................... 55
Pin States during On-Chip Register Field Access Cycle ...................................... 56
Figure 4-1
Figure 4-2
Figure 4-3
Figure 4-4
Figure 4-5
Figure 4-6
Figure 4-7
Figure 4-8
Reset Sequence (Mode 2 or 3, Reset Routine in On-Chip ROM)......................... 61
Reset Sequence (Mode 1)...................................................................................... 62
Block Diagram of Interrupt Controller.................................................................. 66
Hardware Interrupt-Handling Sequence................................................................ 67
Timing of Interrupt Sequence................................................................................ 68
Usage of Stack in Interrupt Handling.................................................................... 74
Example of Damage Caused by Setting an Odd Address in R7 ........................... 75
Example of Deferred Interrupt.............................................................................. 76
Figure 5-1
Port 1 Schematic Diagram..................................................................................... 81
xi