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ii
2.8.6
Power-Down State ................................................................................................ 60
2.9
Basic Timing ...................................................................................................................... 61
2.9.1
Overview ............................................................................................................... 61
2.9.2
On-Chip Memory (ROM, RAM) .......................................................................... 61
2.9.3
On-Chip Supporting Module Access Timing........................................................ 63
2.9.4
External Address Space Access Timing................................................................ 64
2.10
Usage Note ......................................................................................................................... 64
Section 3
MCU Operating Modes ................................................................................. 65
3.1
Overview ............................................................................................................................ 65
3.1.1
Operating Mode Selection .................................................................................... 65
3.1.2
Register Configuration .......................................................................................... 66
3.2
Register Descriptions.......................................................................................................... 66
3.2.1
Mode Control Register (MDCR) .......................................................................... 66
3.2.2
System Control Register (SYSCR) ....................................................................... 67
3.3
Operating Mode Descriptions ............................................................................................ 69
3.3.1
Mode 4 .................................................................................................................. 69
3.3.2
Mode 5 .................................................................................................................. 69
3.3.3
Mode 6 .................................................................................................................. 70
3.3.4
Mode 7 .................................................................................................................. 70
3.4
Pin Functions in Each Operating Mode.............................................................................. 71
3.5
Memory Map in Each Operating Mode.............................................................................. 71
Section 4
Exception Handling ........................................................................................ 73
4.1
Overview ............................................................................................................................ 73
4.1.1
Exception Handling Types and Priority................................................................ 73
4.1.2
Exception Handling Operation.............................................................................. 74
4.1.3
Exception Sources and Vector Table .................................................................... 74
4.2
Reset ................................................................................................................................... 76
4.2.1
Overview ............................................................................................................... 76
4.2.2
Reset Types ........................................................................................................... 76
4.2.3
Reset Sequence...................................................................................................... 77
4.2.4
Interrupts after Reset ............................................................................................. 79
4.2.5
State of On-Chip Supporting Modules after Reset Release .................................. 79
4.3
Traces ................................................................................................................................. 80
4.4
Interrupts ............................................................................................................................ 81
4.5
Trap Instruction .................................................................................................................. 82
4.6
Stack Status after Exception Handling ............................................................................... 83
4.7
Notes on Use of the Stack .................................................................................................. 84
Section 5
Interrupt Controller ......................................................................................... 85
5.1
Overview ............................................................................................................................ 85
5.1.1
Features ................................................................................................................. 85