Table 20-9 (2) Control Signal Timing (S-Mask Versions)
–Preliminary–
Condition B (5-V S-mask):
V
CC
= 5.0 V ±10%, = 2.0 to 16 MHz, V
SS
= 0 V,
T
a
= –20 to +75C (Regular Specifications),
T
a
= –40 to +85C (Wide-Range Specifications)
V
CC
= 3.0 to 5.5 V, = 2.0 to 10 MHz, V
SS
= 0 V,
T
a
= –20 to +75C (Regular Specifications)
Condition C (3-V S-mask):
Condition D (2.7-V S-mask): V
CC
= 2.7 to 5.5 V, = 2.0 to 8 MHz, V
SS
= 0 V,
T
a
= –20 to +75C (Regular Specifications)
Condition D Condition C
8 MHz
Min
Max
200
–
6.0
–
520
–
–
100
132
–
200
–
10
–
50
–
50
–
10
–
50
–
10
–
200
–
Condition B
16 MHz
Min
200
6.0
520
–
132
150
10
50
50
10
50
10
200
10 MHz
Min
200
6.0
520
–
132
200
10
50
50
10
50
10
200
Item
RES setup time
RES pulse width 1
*
RES pulse width 2
*
RES output delay time
RES output pulse width t
RESOW
NMI setup time
NMI hold time
IRQ
0
setup time
IRQ
1
setup time
IRQ
1
hold time
A/D trigger setup time
A/D trigger hold time
NMI pulse width
(for recovery from
software standby
mode)
Crystal oscillator
settling time (reset)
Crystal oscillator
settling time
(software standby)
Note:
*
t
RESW2
applies at power-on and when the RSTOE bit in the reset contol/status register
(RSTCSR) is set to 1. t
RESW1
applies when RSTOE is cleared to 0.
Symbol
t
RESS
t
RESW1
t
RESW2
t
RESD
Max
–
–
–
100
–
–
–
–
–
–
–
–
–
Max
–
–
–
100
–
–
–
–
–
–
–
–
–
Unit
ns
t
cyc
t
cyc
ns
t
cyc
ns
ns
ns
ns
ns
ns
ns
ns
t
NMIS
t
NMIH
t
IRQ0S
t
IRQ1S
t
IRQ1H
t
TRGS
t
TRGH
t
NMIW
t
OSC1
20
–
20
–
20
–
ms
See figure
20-12
See figure
18-1
t
OSC2
10
–
10
–
10
–
ms
See figure
20-7
See figure
20-8
See figure
20-9
See figure
20-22
Test
Conditions
345