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參數(shù)資料
| 型號： | HD74LV595A |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 8-bit Shift Registers with 3-state Outputs |
| 中文描述： | 8位移位寄存器3態(tài)輸出 |
| 文件頁數(shù)： | 11/19頁 |
| 文件大?。?/td> | 82K |
| 代理商： | HD74LV595A |
HD74LV595A
11
Switching Characteristics (cont)
V
CC
= 5.0
±
0.5 V
Ta = 25
°
C
Ta = –40 to 85
°
C
Item
Symbol
Min
Typ
Max
Min
Max
Unit
Test
Conditions
FROM
(Input)
TO
(Output)
Maximum
f
max
135
185
—
115
—
MHz
C
L
= 15 pF
clock
frequency
95
155
—
85
—
C
L
= 50 pF
Propagation
t
PLH
/t
PHL
—
6.2
8.2
1.0
9.4
ns
C
L
= 15 pF
SRCLK
Q
H
'
delay time
—
7.7
10.2
1.0
11.4
C
L
= 50 pF
—
5.4
7.4
1.0
8.5
C
L
= 15 pF
RCLK
Q
A
– Q
H
—
6.9
9.4
1.0
10.5
C
L
= 50 pF
t
PHL
—
5.9
8.0
1.0
9.1
C
L
= 15 pF
SRCLK
Q
H
'
—
7.4
10.0
1.0
11.1
C
L
= 50 pF
Enable time
t
ZH
—
4.8
8.6
1.0
10.0
ns
C
L
= 15 pF
G
Q
A
– Q
H
t
ZL
—
8.3
10.6
1.0
12.0
C
L
= 50 pF
Disable time
t
HZ
—
4.8
8.6
1.0
10.0
ns
C
L
= 15 pF
t
LZ
—
7.6
11.0
1.0
11.0
C
L
= 50 pF
Setup time
t
SU
3.0
—
—
3.0
—
ns
SER before SRCLK
↑
5.0
—
—
5.0
—
SRCLK
↑
before RCLK
↑
5.0
—
—
5.0
—
SRCLR
low before RCLK
↑
2.5
—
—
2.5
—
SRCLR
high (inactive)
before SRCLK
↑
Hold time
t
h
2.0
—
—
2.0
—
ns
SER after SRCLK
↑
0.0
—
—
0.0
—
SRCLK
↑
after RCLK
↑
0.0
—
—
0.0
—
SRCLR
low after RCLK
↑
Pulse width
t
w
5.0
—
—
5.0
—
ns
RCLK high or low
5.0
—
—
5.0
—
SRCLK high or low
5.0
—
—
5.0
—
SRCLR
low
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