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參數(shù)資料
| 型號： | HD74LV595A |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 8-bit Shift Registers with 3-state Outputs |
| 中文描述： | 8位移位寄存器3態(tài)輸出 |
| 文件頁數(shù)： | 9/19頁 |
| 文件大?。?/td> | 82K |
| 代理商： | HD74LV595A |
HD74LV595A
9
Switching Characteristics
V
CC
= 2.5
±
0.2 V
Ta = 25
°
C
Ta = –40 to 85
°
C
Item
Symbol
Min
Typ
Max
Min
Max
Unit
Test
Conditions
FROM
(Input)
TO
(Output)
Maximum
f
max
65
80
—
45
—
MHz
C
L
= 15 pF
clock
frequency
60
70
—
40
—
C
L
= 50 pF
Propagation
t
PLH
/t
PHL
—
11.6
16.4
1.0
19.5
ns
C
L
= 15 pF
SRCLK
Q
H
'
delay time
—
14.8
19.4
1.0
22.5
C
L
= 50 pF
—
10.5
15.3
1.0
18.0
C
L
= 15 pF
RCLK
Q
A
– Q
H
—
13.7
18.3
1.0
21.0
C
L
= 50 pF
t
PHL
—
11.2
16.2
1.0
18.2
C
L
= 15 pF
SRCLK
Q
H
'
—
14.4
19.2
1.0
21.2
C
L
= 50 pF
Enable time
t
ZH
—
10.3
14.8
1.0
17.5
ns
C
L
= 15 pF
G
Q
A
– Q
H
t
ZL
—
12.2
17.7
1.0
20.5
C
L
= 50 pF
Disable time
t
HZ
—
7.6
11.5
1.0
13.5
ns
C
L
= 15 pF
t
LZ
—
14.4
18.2
1.0
19.2
C
L
= 50 pF
Setup time
t
SU
5.5
—
—
5.5
—
ns
SER before SRCLK
↑
10.0
—
—
10.5
—
SRCLK
↑
before
RCLK
↑
10.0
—
—
11.0
—
SRCLR
low before
RCLK
↑
5.0
—
—
5.0
—
SRCLR
high
(inactive) before
SRCLK
↑
Hold time
t
h
2.0
—
—
2.0
—
ns
SER after SRCLK
↑
0.5
—
—
0.5
—
SRCLK
↑
after
RCLK
↑
0.5
—
—
0.5
—
SRCLR
low after
RCLK
↑
Pulse width
t
w
7.0
—
—
7.5
—
ns
RCLK high or low
7.0
—
—
7.5
—
SRCLK high or low
6.0
—
—
6.5
—
SRCLR
low
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|---|---|
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| HD74LV74AFPEL-E | 制造商:Renesas Electronics Corporation 功能描述:HD74LV74AFP-E |
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