9
FN2951.3
October 15, 2008
Capacitance TA = +25°C, Frequency = 1MHz.
SYMBOL
PARAMETER
TEST CONDITIONS
TYP
UNITS
CIN
Input Capacitance
All measurements are referenced to device GND
10
pF
COUT
Output Capacitance
12
pF
AC Electrical Specifications VCC = 5.0V ±10%, TA = -40°C to +85°C (HD-6409-9).
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
UNITS
fC
Clock Frequency
-
16
MHz
tC
Clock Period
-
1/fC
-sec
t1
Bipolar Pulse Width
-
tC+10
-
ns
t3
One-Zero Overlap
-
tC-10
ns
tCH
Clock High Time
f = 16.0MHz
20
-
ns
tCL
Clock Low Time
f = 16.0MHz
20
-
ns
tCE1
Serial Data Setup Time
-
120
-
ns
tCE2
Serial Data Hold Time
-
0
-
ns
tCD2
DCLK to SDO, NVM
-
40
ns
tR2
ECLK to BZO
-
40
ns
tr
Output Rise Time (All except Clock)
From 1.0V to 3.5V, CL = 50pF, Note 8 -
50
ns
tf
Output Fall Time (All except Clock)
From 3.5V to 1.0V, CL = 50pF, Note 8 -
50
ns
tr
Clock Output Rise Time
From 1.0V to 3.5V, CL = 20pF, Note 8 -
11
ns
tf
Clock Output Fall Time
From 3.5V to 1.0V, CL = 20pF, Note 8 -
11
ns
tCE3
ECLK to BZO, BOO
0.5
1.0
DBP
tCE4
CTS Low to BZO, BOO Enabled
0.5
1.5
DBP
tCE5
CTS Low to ECLK Enabled
10.5
11.5
DBP
tCE6
CTS High to ECLK Disabled
-
1.0
DBP
tCE7
CTS High to BZO, BOO Disabled
1.5
2.5
DBP
tCD1
UDI to SDO, NVM
2.5
3.0
DBP
tCD3
RST Low to CDLK, SDO, NVM Low
0.5
1.5
DBP
tCD4
RST High to DCLK, Enabled
0.5
1.5
DBP
tR1
UDI to BZO, BOO
0.5
1.0
DBP
tR3
UDI to SDO, NVM
2.5
3.0
DBP
NOTES:
7. AC testing as follows: f = 4.0MHz, VIH = 70% VCC, VIL = 20% VCC, Speed Select = 16X, VOH ≥ VCC/2, VOL ≤ VCC/2, VCC = 4.5V and 5.5V.
Input rise and fall times driven at 1ns/V, Output load = 50pF.
8. Limits established by characterization and are not production tested.
9. DBP-Data Bit Period, Clock Rate = 16X, one DBP = 16 Clock Cycles; Clock Rate = 32X, one DBP = 32 Clock Cycles.
HD-6409