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8.
LCD Display RAM Map
KING BILLION ELECTRONICS CO., LTD
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公
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HE84760B
HE80004 Series
June 29, 2005
This specification is subject to change without notice. Please contact sales person for the latest version before use.
13
V1.0
The gray-scale LCD driver can be configured to be a 4 gray-scales or black and white display by mask
option MO_GRAY_MODE.
MO_GRAY_MODE[1..0]
00
01
10
11
Gray levels
Not allowed
4
2 (B/W)
2 (B/W)
For 4 gray-scale display, 2-bit of RAM is required for each pixel and 1-bit for black and white display.
For different LCD configuration, the LCD display RAM is arranged differently. The following figure
shows one byte of RAM in different LCD configurations:
0F
xx
0E
xx
0D
xx
0C
xx
0B
xx
0A
xx
09
xx
08
xx
07
xx
06
xx
05
xx
04
xx
03
xx
02
xx
01
xx
00
xx
Black/White
4 Gray scales
Bit 7
SEG7
Bit 6
SEG6
Bit 5
SEG5
Bit 4
SEG4
Bit 3
SEG3
Bit 2
SEG2
Bit 1
SEG1
Bit 0
SEG0
SEG3
SEG2
SEG1
SEG0
The 4 Gray Scale register GRAY0 ~ GRAY3 is the mapping register between the levels selected in RAM
and the real gray scale. In other words, if the content of GRAY0 is 0x03, when value of a certain pixel is
0, the displayed effect will correspond to actual gray level 3. The 4 gray scale display utilizes registers
GRAY0 ~ GRAY3 to select among 32 gray levels to correspond to level 0 ~ 3. Thus user can pick the
gray levels which give the best and most linear effect.
4 Gray Scale registers share a common register address GRAY16. When writing is made to the register, it
will step down to next register in order. The writing sequence can be reset by clearing bit 5 of LCDC
register.
GRAY16
Seq.
1
2
3
4
Field
Bit2
GRAY0
GRAY1
GRAY2
GRAY3
Bit4
Bit3
Bit1
Bit0
Reset
0x00
0x02
0x04
0x06