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KING BILLION ELECTRONICS CO., LTD
駿
億
電
子
股
份
有
限
公
司
HE84G752B
HE80004 Series
January 21, 2005
This specification is subject to change without notice. Please contact sales person for the latest version before use.
13
V0.93
01
10
11
4
2 (B/W)
2 (B/W)
For 4 gray-scale display, 2-bit of RAM is required for each pixel and 4 bit for 16 gray-scale display, 1-bit
for black and white display. For different LCD configuration, the LCD display RAM is arranged
differently. The following figure shows one byte of RAM in different LCD configurations:
0F
xx
0E
xx
0D
xx
0C
xx
0B
xx
0A
xx
09
xx
08
xx
07
xx
06
xx
05
xx
04
xx
03
xx
02
xx
01
xx
00
xx
Black/White
4 Gray scales
16 Gray scales
Bit 7
SEG7
Bit 6
SEG6
Bit 5
SEG5
Bit 4
SEG4
Bit 3
SEG3
Bit 2
SEG2
Bit 1
SEG1
Bit 0
SEG0
SEG3
SEG2
SEG1
SEG0
SEG1
SEG0
The 16 Gray Scale register GRAY0 ~ GRAYF is the mapping register between the levels selected in
RAM and the real gray scale. In other words, if the content of GRAY0 is 0x03, when value of a certain
pixel is 0, the displayed effect will correspond to actual gray level 3. The 16 gray scale display use all 16
registers GRAY0 ~ GRAYF to select among 32 available gray levels to correspond to level 0 ~ 15, while
4 gray scale display utilizes registers GRAY0 ~ GRAY3 to select among 32 gray levels to correspond to
level 0 ~ 3. Thus user can pick the gray levels which give the best and most linear effect.
16 Gray Scale registers share a common register address GRAY16. When writing is made to the register,
it will step down to next register in order. The writing sequence can be reset by clearing bit 5 of LCDC
register.
GRAY16
Seq.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Field
Bit2
GRAY0
GRAY1
GRAY2
GRAY3
GRAY4
GRAY5
GRAY6
GRAY7
GRAY8
GRAY9
GRAYA
GRAYB
GRAYC
GRAYD
GRAYE
GRAYF
Bit4
Bit3
Bit1
Bit0
Reset
0x00
0x02
0x04
0x06
0x08
0x0A
0x0C
0x0E
0x10
0x12
0x14
0x16
0x18
0x1A
0x1C
0x1E