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參數(shù)資料
| 型號(hào)： | HEF4059BT,652 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC COUNTER PROG DIV-BY-N 24-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Logic Packages |
| 標(biāo)準(zhǔn)包裝： | 30 |
| 系列： | 4000B |
| 邏輯類型： | 除以 N |
| 方向： | 下 |
| 元件數(shù)： | 1 |
| 每個(gè)元件的位元數(shù)： | 16 |
| 復(fù)位： | 異步 |
| 計(jì)數(shù)速率： | 20MHz |
| 觸發(fā)器類型： | 正邊沿 |
| 電源電壓： | 4.5 V ~ 15.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SO |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 843 (CN2011-ZH PDF) |
| 其它名稱： | 568-3110-5 933645510652 HEF4059BTD |
January 1995
3
Philips Semiconductors
Product specication
Programmable divide-by-n counter
HEF4059B
LSI
The three mode selection inputs Ka, Kb and Kc determine
the modulus (‘divide-by’ number) of the first and last
counting sections in accordance with Table 1.
Every time the first (fastest) counting section goes through
one cycle, it reduces, by 1, the number that has been
preset (jammed) into the three decades of the intermediate
counting section and into the last counting section (which
consists of flip-flops that are not needed for operating the
first counting section).
For example, in the
÷ 2 mode, only one flip-flop is needed
in the first counting section. Therefore the last (5th)
counting section has three flip-flops that can be preset to a
maximum count of seven with a place value of thousands.
This counting mode is selected when Ka, Kb and Kc are set
to HIGH. In this case input J1 is used to preset the first
counting section and J2 to J4 are used to preset the last
(5th) counting section.
If
÷ 10 mode is desired for the first section, Ka is set HIGH,
Kb to HIGH and Kc to LOW. The jam inputs J1 to J4 are
used to preset the first counting section and there is no last
counting section. The intermediate counting section
consists of three cascaded BCD decade (
÷ 10) counters,
presettable by means of the jam inputs J5 to J16.
When clock pulses are applied to the clock input after a
number
n has been preset into the counter, the counter
counts down until the DETECTION circuit detects the zero
state. At this time the PRESET ENABLE circuit is enabled
to preset again the number
n into the counter and to
produce an output pulse.
The preset of the counter to a desired
÷ n is achieved as
follows:
n = (MODE*) (1000
× decade 5 preset +
100
× decade 4 preset + 10 × decade 3 preset +
1
× decade 2 preset) + decade 1 preset.
* MODE = first counting section divider (10, 8, 5, 4 or 2).
To calculate preset values for any
n count, divide the
n count by the selected mode. The resultant is the
corresponding preset values of the 5th to the 2nd decade
with the remainder being equal to the 1st decade value.
If
n = 8479, and the selected mode = 5, the preset value
= 8479
÷ 5 = 1695 with a remainder of 4, thus the jam
inputs must be set as follows:
preset value
n
mode
----------------
˙
.
=
4
1
596
J1
J2
J3
J4
J5
J6
7
J8
J9
J10
J11
J12
J13
J14
J15
J16
L
HHH
L
H
L
H
L
H
L
HH
L
The mode select inputs permit frequency-synthesizer
channel separations of 10, 12,5, 20, 25 and 50 parts.
These inputs set the maximum value of
n at 9999 (when
the first counting section divides by 5 or 10) or at 15 999
(when the first counting section divides by 8, 4 or 2).
The three decades of the intermediate counting section
can be preset to a binary 15 instead of a binary 9. In this
case the first cycle of a counter consists of 15 count
pulses, the next cycles consisting of 10 count pulses. Thus
the place value of the three decades are still 1, 10 and 100.
For example, in the
÷ 8 mode, the number from which the
intermediate counting section begins to count-down can
be preset to:
3rd
decade:
1500
2nd
decade:
150
1st
decade:
15
1665
The last counting section can be preset to a maximum of
1, with a place value of 1000. The total of these numbers
(2665) times 8 equals 21 320. The first counting section
can be preset to a maximum of 7. Therefore, 21 327 is the
maximum possible count in the
÷ 8 mode. The highest
count of the various modes is shown in Table 1, in the
column entitled ‘extended counter range’. Control inputs
Kb and Kc can be used to initiate and lock the counter in
the ‘master preset’ mode. In this condition the flip-flops in
the counter are preset in accordance with the jam inputs
and the counter remains in that mode as long as Kb and
Kc both remain LOW. The counter begins to run down from
the preset state when a counting mode other than the
‘master preset’ mode is selected. Whenever the ‘master
preset’ mode is used, control signals Kb = L and Kc =L
must be applied for at least 3 full clock pulses. After the
master preset mode inputs have been changed to one of
the counting modes, the next positive-going clock
transition changes an internal flip-flop so that the
count-down can begin at the second positive-going clock
transition. Thus, after a ‘master preset’ mode, there is
always one extra count before the output goes HIGH.
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