參數(shù)資料
型號(hào)： HFCT-5402D
英文描述： 2488 Mb/s Single Mode Fiber Transceiver for SONET OC-48/SDH STM-16 and ATM(應(yīng)用于SONET OC-48/SDH STM-16 和ATM的2488 Mb/s 單模式光收發(fā)器)
中文描述： 2488 Mb / s的掃描隧道顯微鏡的SONET OC-48/SDH單模光纖收發(fā)器- 16和ATM（應(yīng)用于的SONET OC-48/SDH的STM - 16和自動(dòng)柜員機(jī)的2488 Mb / s的單模式光收發(fā)器）
文件頁(yè)數(shù)： 7/20頁(yè)
文件大?。?/td> 1017K
代理商： HFCT-5402D
7
Output Terminations
The receiver DATA and CLOCK
outputs provide Current Mode
Logic (CML) levels. These outputs
are internally ac coupled with 0.1
uF capacitors. Typical output
swings are in the order of 350 mV
for DATA and 300 mV for CLOCK.
Figures 10 and 11 show typical
data and clock waveforms.
It is recommended that the
receiver outputs are connected to
50 ohm transmission lines.
Interfacing with ECL/PECL input
stages is possible provided that
input sensitivities will
accommodate minimum voltage
swings of 200 mV pk-pk.
Signal Detect
The signal detect function is
provided via a single-ended output
and offers low power TTL
capability. Interfacing this node to
other stages requires a high
impedance input typically in the
order of 10 K ohms. Low input
impedance stages are unsuitable.
This node may be left
unconnected if not used.
Hysteresis for the signal detect
function is typically 0.1 dB.
Figure 12 shows a circuit that is
recommended for interfacing the
+5 V TTL SD output into a +3.3 V
LVPECL input. The SD node
comprises a PNP transistor with a
collector resistance of 4.7 K.
Figure 10. Typical Receiver DATA Output 2488 Mb/s.
Figure 11. Typical Receiver CLOCK Output 2488 MHz.
Figure 12.
CDR
IC
4.7 k
HFCT-5404D
16 k
+5 V
SD
LVPECL Input
20 k
+3.3 V
27 k
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