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參數(shù)資料
| 型號： | HFCT-6001D |
| 英文描述： | 622 Mb/s Single Mode Fiber Transceiver for ATM, SONET OC-12/SDH STM-4(應(yīng)用于ATM, SONET OC-12/SDH STM-4的622 Mb/s單模式光收發(fā)器) |
| 中文描述： | 622 Mb / s的對ATM，SONET的OC-12/SDH的STM - 4單模光纖收發(fā)器（應(yīng)用于自動取款機(jī)，SONET的OC-12/SDH的STM - 4的622 Mb / s的單模式光收發(fā)器） |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 177K |
| 代理商： | HFCT-6001D |
11
Table 2. Pin Out Table
(continued)
Pin
Symbol
11
TD+
Functional Description
Transmitter Data In
Terminate this high-speed, differential Transmitter Data input with standard PECL
techniques at the transmitter input pin.
Transmitter Data In Bar
Terminate this high-speed, differential Transmitter Data input with standard PECL
techniques at the transmitter input pin.
Transmitter Power Supply
Provide +5 V dc via the recommended transmitter power supply filter circuit. Locate
the power supply filter circuit as close as possible to the V
CCT
pin.
Receiver Power Supply
Provide +5 V dc via the recommended receiver power supply filter circuit. Locate the
power supply filter circuit as close as possible to the V
CCR
pin.
Signal Detect
Normal input optical levels to the receiver result in a logic “1” output.
Low input optical levels to the receiver result in a fault indication shown by a logic “0”
output.
12
TD-
13
V
CCT
14
V
CCR
15
SD
Signal Detect is a single-ended, low-power, PECL output. Since SD is a low-power
PECL output, complete the interconnection of SD output with other PECL inputs using
a 10 k
pull-down resistor to V
EE
to allow biasing of the interconnection. Do not load
this SD output with standard PECL, 50
to V
CC
-2 V, termination. If Signal Detect
output is not used, leave it open-circuited.
This Signal Detect output can be used to drive a PECL input on an upstream circuit,
such as, Signal Detect input, Loss of Signal-bar input, or to optionally drive the
Lock-to-Reference-bar input (pin 2) of this transceiver.
Retimed Receiver Data Out Bar
Terminate this high-speed, differential, PECL output with standard PECL techniques at
the follow-on device input pin.
Retimed Receiver Data Out
Terminate this high-speed, differential, PECL output with standard PECL techniques at
the follow-on device input pin.
Receiver Signal Ground
Directly connect this pin to receiver signal ground plane.
16
RD-
17
RD+
18
V
EER
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