8
FN3142.8
October 30, 2007
Absolute Maximum Ratings
Thermal Information
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44V
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+22V
V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25V
Digital Input Voltage (VEN, VA) . . . . . (V-) -4V to (V+) +4V or 20mA,
Whichever Occurs First
Analog Signal (VIN, VOUT, Note 5) . . . . . . . . . . (V-) -2V to (V+) +2V Continuous Current, In or Out . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Peak Current, In or Out (Pulsed 1ms, 10% Duty Cycle Max) . 40mA
Operating Conditions
Temperature Ranges
HI-50X-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
HI-50X-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-25°C to +85°C
HI-50X-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +75°C
HI-50X-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Typical Minimum Supply Voltage . . . . . . . . . . . .
±10V or Single 20V
Thermal Resistance (Typical, Note
4)θJA (°C/W) θJC (°C/W)
16 Ld CERDIP Package. . . . . . . . . . . .
85
32
16 Ld SOIC Package . . . . . . . . . . . . . .
115
N/A
16 Ld PDIP Package . . . . . . . . . . . . . .
100
N/A
20 Ld PLCC Package. . . . . . . . . . . . . .
80
N/A
28 Ld CERDIP Package. . . . . . . . . . . .
55
18
28 Ld PDIP Package . . . . . . . . . . . . . .
60
N/A
28 Ld SOIC Package . . . . . . . . . . . . . .
70
N/A
28 Ld PLCC Package. . . . . . . . . . . . . .
70
N/A
Maximum Junction Temperature
Ceramic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
4.
θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. Signals on IN or OUT exceeding V+ or V- are clamped by internal diodes. Limit resulting current to maximum current ratings. If an overvoltage
condition is anticipated (analog input exceeds either power supply voltage), the Intersil HI-546/HI-547/HI-548/HI-549 multiplexers are
recommended.
Electrical Specifications
Supplies = +15V, -15V; VAH (Logic Level High) = 2.4V; VAL (Logic Level Low) = 0.8V,
Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section
PARAMETER
TEST
CONDITIONS
TEMP
(°C)
-2
-4, -5, -9
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
DYNAMIC CHARACTERISTICS
Access Time, tA
25
-
250
500
-
250
-
ns
Full
-
1000
-
1000
ns
Break-Before-Make Delay, tOPEN
25
80
-
25
80
-
ns
Enable Delay (ON), tON(EN)
25
-
250
500
-
250
-
ns
Full
-
1000
-
1000
ns
Enable Delay (OFF), tOFF(EN)
25
-
250
500
-
250
-
ns
Full
-
1000
-
1000
ns
Settling Time, tS
(HI-506 and HI-507)
To 0.1%
25
-
1.2
-
1.2
-
μs
To 0.01%
25
-
2.4
-
2.4
-
μs
Settling Time, tS
(HI-508 and HI-509)
To 0.1%
25
-
360
-
360
-
ns
To 0.01%
25
-
600
-
600
-
ns
Off Isolation
25
-
68
-
68
-
dB
Channel Input Capacitance, CS(OFF)
25
-10
-
-10
-
pF
Channel Output Capacitance, CD(OFF)
HI-506
25
-52
-
-52
-
pF
HI-507
25
-30
-
-30
-
pF
HI-508
25
-17
-
-17
-
pF
HI-509
25
-12
-
-12
-
pF
Digital Input Capacitance, CA
25
-
6
-
6
-
pF
Input to Output Capacitance, CDS(OFF)
25
-0.08
-
-0.08
-
pF
DIGITAL INPUT CHARACTERISTICS
Input Low Threshold, VAL
Full
-
0.8
-
0.8
V
Input High Threshold, VAH
Full
2.4
-
2.4
-
V
HI-506, HI-507, HI-508, HI-509