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參數(shù)資料
| 型號(hào)： | HI3-5701B-9 |
| 廠(chǎng)商： | INTERSIL CORP |
| 元件分類(lèi)： | ADC |
| 英文描述： | 6-Bit, 30MSPS, Flash A/D Converter |
| 中文描述： | 1-CH 6-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDIP18 |
| 封裝： | PLASTIC, DIP-18 |
| 文件頁(yè)數(shù)： | 10/14頁(yè) |
| 文件大?。?/td> | 151K |
| 代理商： | HI3-5701B-9 |
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10
midpoint trim. In general, offset and gain correction can be
done in the preamp circuitry.
Offset Adjustment
The preferred offset correction method is to introduce a DC
component to V
IN
of the converter. An alternate method is to
adjust the V
REF
- input to produce the desired offset
adjustment. The theoretical input voltage to produce the first
transition is
1
/
2
LSB.
V
IN
(0 to 1 transition) =
1
/
2
LSB =
1
/
2
(V
REF
/64) = V
REF
/128.
Gain Adjustment
In general, full scale error correction can be done in the
preamp circuitry by adjusting the gain of the op amp. An
alternate method is to adjust the V
REF
+ input voltage. This
adjustment is performed by setting V
IN
to the 63 to overflow
transition. The theoretical input voltage to produce the
transition is
1
/
2
LSB less than V
REF
+ and is calculated as
follows:
V
IN
(63 to 64 transition) = V
REF
- (V
REF
/128)
= V
REF
(127/128).
To perform the gain trim, first do the offset trim and then
apply the required V
IN
for the 63 to overflow transition. Now
adjust V
REF
+ until that transition occurs on the outputs.
Midpoint Trim
The reference center (
1
/
2
R) is available to the user as the
midpoint of the resistor ladder. The
1
/
2
R point can be used
to improve linearity or create unique transfer functions. The
offset and gain trims should be done prior to adjusting the
midpoint. The theoretical transition from count 31 to 32
occurs at 31.5 LSBs. That voltage is calculated as follows:
V
IN
(31 to 32 transition) = 31.5(V
REF
/64) = V
REF
(63/128).
An adjustable voltage follower can be used to drive the
1
/
2
R
pin. Set V
IN
to the 31 to 32 transition voltage, then adjust the
voltage follower until the transition occurs on the output bits.
Signal Source
A current pulse is present at the analog input (V
IN
) at the
beginning of every sample and auto balance period. The
transient current is due to comparator charging and switch
feed through in the capacitor array. It varies with the
amplitude of the analog input and the sampling rate.
The signal source must be capable of recovering from the
transient prior to the end of the sample period to ensure a
valid signal for conversion. Suitable broad band amplifiers or
buffers which exhibit low output impedance and high output
drive include the HFA-0005, HA-5004, HA-5002, and HA-
5033.
The signal source may drive above or below the power
supply rails, but should not exceed 0.5V beyond the rails or
damage may occur. Input voltages of -0.5V to +
1
/
2
LSB are
converted to all zeros; input voltages of V
REF
+ -
1
/
2
LSB to
V
DD
+ 0.5 are converted to all ones with the Overflow bit set.
Power Supply
The HI-5701 operates nominally from a 5V supply, but will
function from 3V to 6V. The supply should be well regulated
and “clean” of significant noise, especially high frequency
noise. It is recommended that power supply decoupling
capacitors be placed as close to the supply pin as possible.
A combination of 0.01
μ
F ceramic and 10
μ
F tantalum
capacitors is recommended for this purpose as shown in the
test circuit Figure 13.
Reducing Power Consumption
Power dissipation in the HI-5701 is related to clock frequency
and clock duty cycle. For a fixed 50% clock duty cycle, power
may be reduced by lowering the clock frequency. For a given
conversion frequency, power may be reduced by shortening
the Auto Balance
φ
1 portion of the clock duty cycle.
TABLE 4. OUTPUT CODE TABLE
CODE
DESCRIPTION
INPUT VOLTAGE
V
REF
+ = 4V
V
REF
- = 0V
(V)
DECIMAL
COUNT
BINARY OUTPUT CODE
MSB
LSB
OVF
D5
D4
D3
D2
D1
D0
Overflow (OVF)
4.000
127
1
1
1
1
1
1
1
Full Scale (FS)
3.9063
63
0
1
1
1
1
1
1
FS
-
1 LSB
3.8438
62
0
1
1
1
1
1
0
3
/
4
FS
2.9688
48
0
1
1
0
0
0
0
HI-5701
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相關(guān)代理商/技術(shù)參數(shù) |
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