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參數(shù)資料
| 型號(hào)： | HI3026EVAL |
| 廠商： | Intersil Corporation |
| 英文描述： | 8-Bit, 120 MSPS, Flash A/D Converter |
| 中文描述： | 8位，120 MSPS的，閃光的A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 9/17頁 |
| 文件大?。?/td> | 207K |
| 代理商： | HI3026EVAL |
4-1370
Notes on Operation
The HI3026 is a high-speed A/D converter which is capable
of TTL, ECL and PECL level clock input. Characteristic
impedance should be properly matched to ensure optimum
performance during high-speed operation.
The power supply and grounding have a profound influence
on converter performance. The power supply and ground-
ing method are particularly important during high-speed
operation. General points for caution are as follows:
- The ground pattern should be as large as possible. It is
recommended to make the power supply and ground
patterns wider at an inner layer using a multi-layer
board.
- To prevent interference between AGND and DGND and
between AV
CC
and DV
CC
, make sure the respective pat-
terns are separated. To prevent a DC offset in the power
supply pattern, connect the AV
CC
and DV
CC
lines at one
point each, via a ferrite-bead filter. Shorting the AGND
and DGND patterns in one place immediately under the
A/D converter improves A/D converter performance.
- Ground the power supply pins (AV
CC
, DV
CC1
, DV
CC2
,
DV
EE3
) as close to each pin as possible with a 0.1
μ
F or
larger ceramic chip capacitor. (Connect the AV
CC
pin to
the AGND pattern and the DV
CC1
, DV
CC2
, DV
EE3
pins
to the DGND pattern).
- The digital output wiring should be as short as possible.
If the digital output wiring is long, the wiring capacitance
will increase, deteriorating the output slew rate and
resulting in reflection to the output waveform since the
original output slew rate is quite fast.
The analog input pin V
IN
has an input capacitance of
approximately 21pF. To drive the A/D converter with
proper frequency response, it is necessary to prevent per-
formance deterioration due to parasitic capacitance or
parasitic inductance by using a large capacity drive circuit;
keeping wiring as short as possible, and using chip parts
for resistors and capacitors, etc.
The V
RT
and V
RB
pins must have adequate bypass to pro-
tect them from high-frequency noise. Bypass them to
AGND with approximately 1
μ
F tantal capacitor and, 0.1
μ
F
capacitor. At this time, approximately DGND3 - 1.2V voltage
is generated. However, this is not recommended for use as
threshold voltage V
BB
as it is too weak.
When the digital input level is ECL or PECL level, ***/E pins
should be used and ***/T pins left open. When the digital
input level is TTL, ***/T pins should be used and III/E pins
left open.
TABLE 1. A/D CODE TABLE
V
IN
V
RT
STEP
INV
1
0
D7
D0
D7
D0
255
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
254
1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1
V
RM2
128
1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
127
0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0
1
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0
V
RB
0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Test Circuits
FIGURE 4. CURRENT CONSUMPTION MEASUREMENT
CIRCUIT
FIGURE 5. INTEGRAL LINEARITY ERROR/DIFFERENTIAL
LINEARITY ERROR MEASUREMENT CIRCUIT
V
RT
V
IN
V
RB
AV
CC
DV
CC1
DV
CC2
DGND2
DGND1
AGND
DGND3
CLK/E
DV
EE3
4V
1.95V
2V
5MHz PECL
A
A
5V
5V
I
CC
I
EE
A < B A > B
COMPARATOR
A8
TO
A1
B8
TO
B1
B0
A0
HI3026
BUFFER
CONTROLLER
DVM
000...00
TO
111..10
V
IN
8
“0”
8
“1”
-V
+V
S2
S1: ON WHEN A < B
S2: ON WHEN A > B
S1
-
+
HI3026
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| HI-303/883 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Dual SPDT CMOS Analog Switch |
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| HI3-0300-5 | 制造商:Harris Corporation 功能描述: |
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