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參數(shù)資料
| 型號： | HI5766KCA |
| 廠商： | Intersil |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10-BIT 60MSPS 28-SSOP |
| 標(biāo)準(zhǔn)包裝： | 48 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 60M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 8 |
| 功率耗散（最大）： | 260mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP/QSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個單端，單極；1 個差分，雙極 |
11
Detailed Description
Theory of Operation
The HI5766 is a 10-bit fully differential sampling pipeline A/D
converter with digital error correction logic. Figure 24 depicts
the circuit for the front end differential-in-differential-out sample-
and-hold (S/H). The switches are controlled by an internal
sampling clock which is a non-overlapping two phase signal
,
φ
1
and
φ
2, derived from the master sampling clock. During the
sampling phase,
φ
1, the input signal is applied to the sampling
capacitors, CS. At the same time the holding capacitors, CH,
are discharged to analog ground. At the falling edge of
φ
1 the
input signal is sampled on the bottom plates of the sampling
capacitors. In the next clock phase,
φ
2, the two bottom plates of
the sampling capacitors are connected together and the
holding capacitors are switched to the op amp output nodes.
The charge then redistributes between CS and CH completing
one sample-and-hold cycle. The front end sample-and-hold
output is a fully-differential, sampled-data representation of the
analog input. The circuit not only performs the sample-and-hold
function but will also convert a single-ended input to a fully-
differential output for the converter core. During the sampling
phase, the VIN pins see only the on-resistance of a switch and
CS. The relatively small values of these components result in a
typical full power input bandwidth of 250MHz for the converter.
As illustrated in the functional block diagram and the timing
diagram in Figure 1, eight identical pipeline subconverter
stages, each containing a two-bit flash converter and a
FIGURE 21. DC BIAS VOLTAGE (VDC) vs TEMPERATURE
FIGURE 22. 2048 POINT FFT PLOT
FIGURE 23. 2048 POINT FFT PLOT
Typical Performance Curves (Continued)
3.30
3.00
-40
-20
0
204060
80
TEMPERATURE (oC)
V
DC
(V
)
3.20
3.10
FREQUENCY (BIN)
OUTPUT
LEVE
L
(dB)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
100
200
300
400
500
600
700
800
900
1023
fS = 60 MSPS
TA = 25
oC
fIN = 1MHz
FREQUENCY (BIN)
O
UTPUT
LEVEL
(dB
)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
100
200
300
400
500
600
700
800
900
1023
fS = 60 MSPS
TA = 25
oC
fIN = 10MHz
-
+
-
CH
CS
CH
VIN+
VOUT+
VOUT-
VIN-
φ1
φ
1
φ1
φ
2
φ
1
φ1
φ
1
FIGURE 24. ANALOG INPUT SAMPLE-AND-HOLD
HI5766
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HI5766KCAZ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC A/D 10-BIT 60MSPS 28 SSOP COM TEMP RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| HI5766KCB | 功能描述:CONV A/D 10BIT 60MSPS 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| HI5766KCBS2503 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HI5766KCBZ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 28 COMTEMP A/D 10BIT 60MSPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| HI5767 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:10-Bit, 20/40/60MSPS A/D Converter with Internal Voltage Reference |
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