fS =Internal Clock, fIN
參數(shù)資料
型號(hào): HI5812JIBZ-T
廠商: Intersil
文件頁(yè)數(shù): 11/16頁(yè)
文件大?。?/td> 0K
描述: ADC 12BIT SAMPL TRK&HOLD 24-SOIC
標(biāo)準(zhǔn)包裝: 1,000
位數(shù): 12
采樣率(每秒): 50k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 25mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 24-SOIC
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個(gè)單端,單極
4
Spurious Free Dynamic Range,
SFDR
J
fS =Internal Clock, fIN = 1kHz
fS = 750kHz, fIN = 1kHz
-
-75.4
-75.1
-
dB
K
fS = Internal Clock, fIN = 1kHz
fS = 750kHz, fIN = 1kHz
-
-80.9
-79.6
-
dB
ANALOG INPUT
Input Current, Dynamic
At VIN = VREF+, 0V
-
±50
±100
-
±100
A
Input Current, Static
Conversion Stopped
-
±0.4
±10
-
±10
A
Input Bandwidth -3dB
-
1
-
MHz
Reference Input Current
-
160
-
A
Input Series Resistance, RS
In Series with Input CSAMPLE
-
420
-
W
Input Capacitance, CSAMPLE
During Sample State
-
380
-
pF
Input Capacitance, CHOLD
During Hold State
-
20
-
pF
DIGITAL INPUTS OEL, OEM, STRT
High-Level Input Voltage, VIH
2.4
-
2.4
-
V
Low-Level Input Voltage, VIL
-
0.8
-
0.8
V
Input Leakage Current, IIL
Except CLK, VIN = 0V, 5V
-
±10
-
±10
A
Input Capacitance, CIN
-
10
-
pF
DIGITAL OUTPUTS
High-Level Output Voltage, VOH
ISOURCE = -400A
4.6
-
4.6
-
V
Low-Level Output Voltage, VOL
ISINK = 1.6mA
-
0.4
-
0.4
V
Three-State Leakage, IOZ
Except DRDY, VOUT = 0V, 5V
-
±10
-
±10
A
Output Capacitance, COUT
Except DRDY
-
20
-
pF
CLOCK
High-Level Output Voltage, VOH
ISOURCE = -100A (Note 2)
4
-
4
-
V
Low-Level Output Voltage, VOL
ISINK = 100A (Note 2)
-
1
-
1
V
Input Current
CLK Only, VIN = 0V, 5V
-
±5
-
±5
mA
TIMING
Conversion Time (tCONV + tACQ)
(Includes Acquisition Time)
20
-
20
-
s
Clock Frequency
Internal Clock, (CLK = Open)
200
300
400
150
500
kHz
External CLK (Note 2)
0.05
2
1.5
0.05
1.5
MHz
Clock Pulse Width, tLOW, tHIGH
External CLK (Note 2)
100
-
100
-
ns
Aperture Delay, tDAPR
(Note 2)
-
35
50
-
70
ns
Clock to Data Ready Delay, tD1DRDY
(Note 2)
-
105
150
-
180
ns
Clock to Data Ready Delay, tD2DRDY
(Note 2)
-
100
160
-
195
ns
Start Removal Time, tRSTRT
(Note 2)
75
30
-
75
-
ns
Start Setup Time, tSUSTRT
(Note 2)
85
60
-
100
-
ns
Start Pulse Width, tWSTRT
(Note 2)
10
4
-
15
-
ns
Start to Data Ready Delay, tD3 DRDY
(Note 2)
-
65
105
-
120
ns
Electrical Specifications
VDD = VAA+ = 5V, VREF+ = +4.608V, VSS = VAA- = VREF- = GND, CLK = External 750kHz,
Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
25oC
-40oC TO 85oC
UNITS
MIN
TYP
MAX
MIN
MAX
HI5812
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