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參數(shù)資料
| 型號(hào)： | HI5812JIBZ-T |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 3/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | ADC 12BIT SAMPL TRK&HOLD 24-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 50k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 25mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)單端，單極 |
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11
A simplified analog input model is presented in Figure 19.
During tracking, the A/D input (VIN) typically appears as a
380pF capacitor being charged through a 420
internal
switch resistance. The time constant is 160ns. To charge this
capacitor from an external “zero
” source to 0.5 LSB
(1/8192), the charging time must be at least 9 time constants
or 1.4
s. The maximum source impedance (RSOURCE Max)
for a 4
s acquisition time settling to within 0.5LSB is 750.
If the clock frequency was slower, or the converter was not
restarted immediately (causing a longer sample time), a
higher source impedance could be tolerated.
Reference Input
The reference input VREF+ should be driven from a low
impedance source and be well decoupled.
As shown in Figure 20, current spikes are generated on the
reference pin during each bit test of the successive
approximation part of the conversion cycle as the charge-
balancing capacitors are switched between VREF- and
VREF+ (clock periods 5 - 14). These current spikes must
settle completely during each bit test of the conversion to not
degrade the accuracy of the converter. Therefore VREF+
and VREF- should be well bypassed. Reference input VREF-
is normally connected directly to the analog ground plane. If
VREF- is biased for nulling the converters offset it must be
stable during the conversion cycle.
The HI5812 is specified with a 4.608V reference, however, it
will operate with a reference down to 3V having a slight
degradation in performance. A typical graph of accuracy vs
reference voltage is presented.
Full Scale and Offset Adjustment
In many applications the accuracy of the HI5812 would be
sufficient without any adjustments. In applications where
accuracy is of utmost importance full scale and offset errors
may be adjusted to zero.
The VREF+ and VREF- pins reference the two ends of the
analog input range and may be used for offset and full scale
adjustments. In a typical system the VREF- might be
returned to a clean ground, and the offset adjustment done
on an input amplifier. VREF+ would then be adjusted to null
out the full scale error. When this is not possible, the VREF-
input can be adjusted to null the offset error, however,
VREF- must be well decoupled.
Full scale and offset error can also be adjusted to zero in the
signal conditioning amplifier driving the analog input (VIN).
Control Signal
The HI5812 may be synchronized from an external source
by using the STRT (Start Conversion) input to initiate
conversion, or if STRT is tied low, may be allowed to free
run. Each conversion cycle takes 15 clock periods.
The input is tracked from clock period 1 through period 3,
then disconnected as the successive approximation takes
place. After the start of the next period 1 (specified by tD
data), the output is updated.
The DRDY (Data Ready) status output goes high (specified
by tD1DRDY) after the start of clock period 1, and returns
low (specified by tD2DRDY) after the start of clock period 2.
The 12 data bits are available in parallel on three-state bus
driver outputs. When low, the OEM input enables the most
significant byte (D4 through D11) while the OEL input
enables the four least significant bits (D0 - D3). tEN and tDIS
specify the output enable and disable times.
If the output data is to be latched externally, either the
trailing edge of data ready or the next falling edge of the
clock after data ready goes high can be used.
When STRT input is used to initiate conversions, operation
is slightly different depending on whether an internal or
external clock is used.
Figure 3 illustrates operation with an internal clock. If the
STRT signal is removed (at least tRSTRT) before clock
period 1, and is not reapplied during that period, the clock
will shut off after entering period 2. The input will continue to
track and the DRDY output will remain high during this time.
A low signal applied to STRT (at least tWSTRT wide) can
now initiate a new conversion. The STRT signal (after a
delay of (tDSTRT)) causes the clock to restart.
RSOURCE
VIN
RSW ≈ 420
CSAMPLE ≈ 380pF
R
SOURCE(MAX)
t
ACQ
–
C
SAMPLEIn 2
N1
+
()
–
[]
-------------------------------------------------------------- R
SW
–
=
FIGURE 19. ANALOG INPUT MODEL IN TRACK MODE
20mA
10mA
0mA
5V
0V
5V
0V
IREF+
CLK
DRDY
2
s/DIV.
CONDITIONS: VDD = VAA+ = 5.0V, VREF+ = 4.608V,
VIN = 2.3V, CLK = 750kHz, TA = 25
oC
FIGURE 20. TYPICAL REFERENCE INPUT CURRENT
HI5812
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| HI5860IBZ | CONV D/A 12-BIT 130MSPS 28-SOIC |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HI5812JIJ | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 20 Microsecond, 12-Bit, Sampling A/D Converter with Internal Track and Hold |
| HI5812JIP | 功能描述:ADC 12BIT 50KSPS 1.5LSB 24-DIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| HI5812JIPS2268 | 制造商:Harris Corporation 功能描述: |
| HI5812JIPZ | 功能描述:IC ADC 12BIT 50KSPS LP HS 24DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| HI5812JIPZ | 制造商:Intersil Corporation 功能描述:A/D CONVERTER (A-D) IC |
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