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參數(shù)資料
| 型號： | HIP6604B |
| 廠商： | Intersil Corporation |
| 元件分類： | FPGA |
| 英文描述： | FPGA 2000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 同步整流降壓MOSFET驅(qū)動器 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大小： | 346K |
| 代理商： | HIP6604B |
7
FN9072.7
July 20, 2005
be performed to ensure safe operation at the desired
frequency for the selected MOSFETs. The power dissipated
by the driver is approximated as:
where f
sw
is the switching frequency of the PWM signal. V
U
and V
L
represent the upper and lower gate rail voltage. Q
U
and Q
L
is the upper and lower gate charge determined by
MOSFET selection and any external capacitance added to
the gate pins. The I
DDQ
V
CC
product is the quiescent power
of the driver and is typically 30mW.
The power dissipation approximation is a result of power
transferred to and from the upper and lower gates. But, the
internal bootstrap device also dissipates power on-chip
during the refresh cycle. Expressing this power in terms of
the upper MOSFET total gate charge is explained below.
The bootstrap device conducts when the lower MOSFET or
its body diode conducts and pulls the PHASE node toward
GND. While the bootstrap device conducts, a current path is
formed that refreshes the bootstrap capacitor. Since the
upper gate is driving a MOSFET, the charge removed from
the bootstrap capacitor is equivalent to the total gate charge
of the MOSFET. Therefore, the refresh power required by
the bootstrap capacitor is equivalent to the power used to
charge the gate capacitance of the MOSFET.
where Q
LOSS
is the total charge removed from the bootstrap
capacitor and provided to the upper gate load.
The 1.05 factor is a correction factor derived from the
following characterization. The base circuit for characterizing
the drivers for different loading profiles and frequencies is
provided. C
U
and C
L
are the upper and lower gate load
capacitors. Decoupling capacitors [0.15
μ
F] are added to the
PVCC and VCC pins. The bootstrap capacitor value is
0.01
μ
F.
In Figure 1, C
U
and C
L
values are the same and frequency
is varied from 50kHz to 2MHz. PVCC and VCC are tied
together to a +12V supply. Curves do exceed the 800mW
cutoff, but continuous operation above this point is not
recommended.
Figure 2 shows the dissipation in the driver with 3nF loading
on both gates and each individually. Note the higher upper
gate power dissipation which is due to the bootstrap device
refresh cycle. Again PVCC and VCC are tied together and to
a +12V supply.
Test Circuit
The impact of loading on power dissipation is shown in
Figure 3. Frequency is held constant while the gate capacitors
are varied from 1nF to 5nF. VCC and PVCC are tied together
and to a +12V supply. Figures 4, 5 and 6 show the same
characterization for the HIP6603B with a +5V supply on PVCC
and VCC tied to a +12V supply.
Since both upper and lower gate capacitance can vary,
Figure 8 shows dissipation curves versus lower gate
capacitance with upper gate capacitance held constant at three
different values. These curves apply only to the HIP6601B due
to power supply configuration.
P
1.05f
sw
3
2
--
V
U
Q
U
V
L
Q
L
+
I
DDQ
VCC
+
=
P
REFRESH
1
2
--
f
SW
Q
LOSS
V
PVCC
1
2
--
f
SW
Q
U
V
U
=
=
BOOT
UGATE
PHASE
LGATE
PWM
PVCC
GND
VCC
0.15
μ
F
0.15
μ
F
100k
2N7002
2N7002
C
L
0.01
μ
F
C
U
+5V OR +12V
+12V
H
+5V OR +12V
FIGURE 1. POWER DISSIPATION vs FREQUENCY
1000
800
600
400
200
0
500
1000
1500
2000
P
FREQUENCY (kHz)
C
U
= C
L
= 3nF
VCC = PVCC = 12V
C
U
= C
L
= 1nF
C
U
= C
L
= 2nF
C
U
= C
L
= 4nF
C
U
= C
L
= 5nF
FIGURE 2. 3nF LOADING PROFILE
1000
800
600
400
200
0
500
1000
1500
2000
P
FREQUENCY (kHz)
C
U
= C
L
= 3nF
VCC = PVCC = 12V
C
U
= 3nF
C
L
= 0nF
C
U
= 0nF
C
L
= 3nF
HIP6601B, HIP6603B, HIP6604B
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| HIP6604BCR | 功能描述:IC DRIVER MOSF SYNC BUCK 16-QFN RoHS:否 類別:集成電路 (IC) >> PMIC - MOSFET，電橋驅(qū)動器 - 外部開關(guān) 系列:- 標(biāo)準(zhǔn)包裝:50 系列:- 配置:低端 輸入類型:非反相 延遲時(shí)間:40ns 電流 - 峰:9A 配置數(shù):1 輸出數(shù):1 高端電壓 - 最大（自引導(dǎo)啟動）:- 電源電壓:4.5 V ~ 35 V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:TO-263-6，D²Pak（5 引線+接片），TO-263BA 供應(yīng)商設(shè)備封裝:TO-263 包裝:管件 |
| HIP6604BCR-T | 功能描述:IC DRIVER MOSF SYNC BUCK 16-QFN RoHS:否 類別:集成電路 (IC) >> PMIC - MOSFET，電橋驅(qū)動器 - 外部開關(guān) 系列:- 標(biāo)準(zhǔn)包裝:50 系列:- 配置:低端 輸入類型:非反相 延遲時(shí)間:40ns 電流 - 峰:9A 配置數(shù):1 輸出數(shù):1 高端電壓 - 最大（自引導(dǎo)啟動）:- 電源電壓:4.5 V ~ 35 V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:TO-263-6，D²Pak（5 引線+接片），TO-263BA 供應(yīng)商設(shè)備封裝:TO-263 包裝:管件 |
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| HIP6604CR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Synchronous Rectified Buck MOSFET Drivers |
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