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參數(shù)資料
| 型號(hào)： | HM-6504883 |
| 廠商： | Intersil Corporation |
| 英文描述： | 4096 x 1 CMOS RAM |
| 中文描述： | 4096 × 1 CMOS存儲(chǔ)器 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大小： | 167K |
| 代理商： | HM-6504883 |
6-139
Timing Waveforms
The address information is latched in the on-chip registers
on the falling edge of E (T = 0). Minimum address set up and
hold time requirements must be met. After the required hold
time, the addresses may change state without affecting
device operation. During time (T = 1) the output becomes
enabled but the data is not valid until during time (T = 2). W
must remain high for the read cycle. After the output data
has been read, E may return high (T = 3). This will disable
the output buffer and all input, and ready the RAM for the
next memory cycle (T = 4).
TRUTH TABLE
TIME REFERENCE
INPUTS
OUTPUT
FUNCTION
E
W
A
Q
-1
H
X
X
Z
Memory Disabled
0
H
V
Z
Cycle Begins, Addresses are Latched
1
L
H
X
X
Output Enabled
2
L
H
X
V
Output Valid
3
H
X
V
Read Accomplished
4
H
X
X
Z
Prepare for Next Cycle (Same as -1)
5
H
V
Z
Cycle Ends, Next Cycle Begins (Same as 0)
A
(7)
NEXT ADD
TAVEL
(8)
TELAX
(7)
TAVEL
(4) TEHQZ
HIGH Z
VALID DATA OUTPUT
(3)
TELQX
HIGH Z
E
Q
W
HIGH
-1
TIME
0
1
2
3
4
5
REFERENCE
(6)
TEHEL
TELEL (18)
(5)
TELEH
(6)
TEHEL
(1) TELQV
FIGURE 1. READ CYCLE
ADD VALID
HM-6504/883
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