6-134
March 1997
HM-6504/883
4096 x 1 CMOS RAM
Features
This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
Low Power Standby. . . . . . . . . . . . . . . . . . . 125
μ
W Max
Low Power Operation . . . . . . . . . . . . . 35mW/MHz Max
Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min
TTL Compatible Input/Output
Three-State Output
Standard JEDEC Pinout
Fast Access Time. . . . . . . . . . . . . . . . . . 120/200ns Max
18 Pin Package for High Density
On-Chip Address Register
Gated Inputs - No Pull Up or Pull Down Resistors
Required
Description
The HM-6504/883 is a 4096 x 1 static CMOS RAM
fabricated using self-aligned silicon gate technology. The
device utilizes synchronous circuitry to achieve high perfor-
mance and low power operation.
On-chip latches are provided for addresses, data input and
data output allowing efficient interfacing with microprocessor
systems. The data output can be forced to a high impedance
state for use in expanded memory arrays.
Gated inputs allow lower operating current and also elimi-
nate the need for pull up or pull down resistors. The
HM-6504/883 is a fully static RAM and may be maintained in
any state for an indefinite period of time.
Data retention supply voltage and supply current are guaran-
teed over temperature.
Ordering Information
Pinout
HM-6504/883 (CERDIP)
TOP VIEW
PACKAGE
TEMPERATURE RANGE
-55
o
C to +125
o
C
200ns
300ns
PKG. NO
CERDIP
HM1-6504B/883
HM1-6504/883
F18.3
PIN
DESCRIPTION
A
Address Input
E
Chip Enable
W
Write Enable
D
Data Input
Q
Data Output
10
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1
VCC
A7
A8
A9
A10
A11
D
A6
E
A0
A1
A2
A3
A4
A5
W
Q
GND
File Number
2993.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Intersil Corporation 1999