參數(shù)資料
型號: HM514260CLTT-7
廠商: Hitachi,Ltd.
英文描述: 262,144-word x 16-bit Dynamic Random Access Memory
中文描述: 262,144字× 16位動態(tài)隨機存取存儲器
文件頁數(shù): 25/27頁
文件大?。?/td> 260K
代理商: HM514260CLTT-7
HM514260C, HM51S4260C Series
25
Self Refresh Cycle
RAS
Address
Dout
t
RP
t
RASS
t
RPS
t
RPC
t
CPN
t
T
t
CSR
t
CHS
t
CRP
t
OFF1
High-Z
* WE, OE
UCAS
LCAS
: H or L
The low self refresh current is achieved by introducing extremely long internal refresh cycle. Therefore
some care needs to be taken on the refresh.
1. Please do not use t
RASS
timing, 10 μs
t
RASS
100 μs. During this period, the device is in
transition state from normal operation mode to self refresh mode. If t
RASS
100 μs, then
RAS
precharge time should use t
RPS
instead of t
RP
.
If you use
RAS
only refresh or CBR burst refresh mode in normal read/write cycle, 512 cycles
of distributed CBR refresh with 15.6 μs interval should be executed within 8 ms immediately
after exiting from and before entering into the self refresh mode.
If you use distributed CBR refresh mode with 15.6 μs interval in normal read/write cycle, CBR
refresh should be executed within 15.6 μs immediately after exiting from and before entering
into self refresh mode.
Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from
self refresh mode, all memory cells need to be refreshed before re-entering the self refresh
mode again.
2.
3.
4.
相關PDF資料
PDF描述
HM514260CLTT-8 262,144-word x 16-bit Dynamic Random Access Memory
HM514260CTT-6 262,144-word x 16-bit Dynamic Random Access Memory
HM514260CTT-6R 262,144-word x 16-bit Dynamic Random Access Memory
HM514260CTT-7 262,144-word x 16-bit Dynamic Random Access Memory
HM514260CTT-8 262,144-word x 16-bit Dynamic Random Access Memory
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