參數(shù)資料
型號(hào)： HM514400B
廠商： Hitachi,Ltd.
英文描述： 1,048,576-word X 4-bit Dynamic Random Access Memory
中文描述： 1,048,576字× 4位動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器
文件頁(yè)數(shù)： 13/27頁(yè)
文件大?。?/td> 235K
代理商： HM514400B
Notes: 1. AC measurements assume t
T
= 5 ns.
2. Assumes that t
RCD
≤
t
RCD
(max) and t
RAD
≤
t
RAD
(max). If t
RCD
or t
RAD
is greater than the
maximum recommended value shown in this table, t
RAC
exceeds the value shown.
3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF.
4. Assumes that t
RCD
≥
t
RCD
(max) and t
RAD
≤
t
RAD
(max).
5. Assumes that t
RCD
≤
t
RCD
(max) and t
RAD
≥
t
RAD
(max).
6. t
OFF
(max) defines the time at which the output achieves the open circuit condition and is not
referred to output voltage levels.
7. V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals. Also,
transition times are measured between V
IH
and V
IL
.
8. Operation with the t
RCD
(max) limit insures that t
RAC
(max) can be met, t
RCD
(max) is specified
as a reference point only, if t
RCD
is greater than the specified t
RCD
(max) limit, then access time
is controlled exclusively by t
CAC
.
9. Operation with the t
RAD
(max) limit insures that t
RAC
(max) can be met, t
RAD
(max) is specified
as a reference point only, if t
RAD
is greater than the specified t
RAD
(max) limit, then access time
is controlled exclusively by t
AA
.
10.t
WCS
, t
RWD
, t
CWD
, t
CPW
and t
AWD
are not restrictive operating parameters. They are included in
the data sheet as electrical characteristics only; if t
WCS
≥
t
WCS
(min), the cycle is an early write
cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle;
if t
RWD
≥
t
RWD
(min), t
CWD
≥
t
CWD
(min), t
CPW
≥
t
CPW
(min) and t
AWD
≥
t
AWD
(min), the cycle is a
read-modify-write and the data output will contain data read from the selected cell; if neither of
the above sets of conditions is satisfied, the condition of the data out (at access time) is
indeterminate.
11.These parameters are referred to
CAS
leading edge in an early write cycle and to
WE
leading
edge in a delayed write or read-modify-write cycle.
12.t
RASC
defines
RAS
pulse width in fast page mode cycles.
13.Access time is determined by the longest among t
AA
, t
CAC
and t
ACP
.
14.An initial pause of 100
μ
s is required after power up followed by a minimum of eight initialization
cycles (
RAS
-only refresh cycle or
CAS
-before-
RAS
refresh cycle). If the internal refresh counter
is used, a minimum of eight
CAS
-before-
RAS
refresh cycles is required.
15.In delayed write or read-modify-write cycles,
OE
must disable output buffer prior to applying data
to the device.
16.Test mode operation specified in this data sheet is 2-bit test function controlled by control
address bits - - - CA0. This test mode operation can be performed by
WE
-and-
CAS
-before-
RAS
(WCBR) refresh cycle. Refresh during test mode operation will be performed by normal read
cycles or by WCBR refresh cycles. When the state of two test bits accord each other, the
condition of the output data is high level. When the state of test bits do not accord, the condition
of the output data is low level. In order to end this test mode operation, perform a
RAS
-only
refresh cycle or a
CAS
-before-
RAS
refresh cycle.
17.In a test mode read cycle, the value of t
RAC
, t
AA
, t
CAC
, t
OAC
and t
ACP
is delayed for 2 ns to 5 ns
for the specified value. These parameters should be specified in test mode cycles by adding the
above value to the specified value in this data sheet.
18.Either t
RCH
or t
RRH
must be satisfied
19.t
RAS
(min) = t
RWD
(min) + t
RWL
(min) + t
T
in read-modify-write cycle.
20.t
CAS
(min) = t
CWD
(min) + t
CWL
(min) + t
T
in read-modify-write cycle.
13
HM514400B/BL, HM514400C/CL Series
相關(guān)PDF資料
PDF描述
HM514400BL 1,048,576-word X 4-bit Dynamic Random Access Memory
HM514400C 1,048,576-word X 4-bit Dynamic Random Access Memory
HM514400CL 1,048,576-word X 4-bit Dynamic Random Access Memory
HM5164165F 64M EDO DRAM (4-Mword x 16-bit) 8k refresh/4k refresh
HM5164165FJ-5 64M EDO DRAM (4-Mword x 16-bit) 8k refresh/4k refresh
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HM514400BL 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:1,048,576-word X 4-bit Dynamic Random Access Memory
HM514400BLR-6 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 Fast Page Mode DRAM
HM514400BLR-7 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 Fast Page Mode DRAM
HM514400BLR-8 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 Fast Page Mode DRAM
HM514400BLRR-6 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 Fast Page Mode DRAM
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