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參數(shù)資料
| 型號： | HM5259805BTD-A6 |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword 】 16-bit 】 4-bank/16-Mword 】 8-bit 】 4-bank /32-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM |
| 中文描述： | 64M X 8 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 14/63頁 |
| 文件大?。?/td> | 368K |
| 代理商： | HM5259805BTD-A6 |
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HM5259165B/HM5259805B/HM5259405B-75/A6
Data Sheet E0118H10
14
Self-refresh entry [SELF]:
When this command is input during the IDLE state, the SDRAM starts self-
refresh operation. After the execution of this command, self-refresh continues while CKE is Low. Since self-
refresh is performed internally and automatically, external refresh operations are unnecessary.
Power down mode entry:
When this command is executed during the IDLE state, the SDRAM enters power
down mode. In power down mode, power consumption is suppressed by cutting off the initial input circuit.
Self-refresh exit:
When this command is executed during self-refresh mode, the SDRAM can exit from self-
refresh mode. After exiting from self-refresh mode, the SDRAM enters the IDLE state.
Power down exit:
When this command is executed at the power down mode, the SDRAM can exit from
power down mode. After exiting from power down mode, the SDRAM enters the IDLE state.
Function Truth Table
The following table shows the operations that are performed when each command is issued in each mode of
the SDRAM.
The following table assumes that CKE is high.
Current state
CS
RAS
CAS
WE
Address
Command
Operation
Precharge
H
×
×
×
×
×
DESL
Enter IDLE after t
RP
Enter IDLE after t
RP
ILLEGAL*
4
L
H
H
H
NOP
L
H
L
H
BA, CA, A10 READ/READ A
L
H
L
L
BA, CA, A10 WRIT/WRIT A
ILLEGAL*
4
L
L
H
H
BA, RA
ACTV
ILLEGAL*
4
L
L
H
L
BA, A10
PRE, PALL
NOP*
6
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
Idle
H
×
×
×
×
×
DESL
NOP
L
H
H
H
NOP
NOP
L
H
L
H
BA, CA, A10 READ/READ A
ILLEGAL*
5
L
H
L
L
BA, CA, A10 WRIT/WRIT A
ILLEGAL*
5
L
L
H
H
BA, RA
ACTV
Bank and row active
L
L
H
L
BA, A10
PRE, PALL
NOP
L
L
L
H
×
REF, SELF
Refresh
L
L
L
L
MODE
MRS
Mode register set
相關PDF資料 |
PDF描述 |
|---|---|
| HM5259805B-75 | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT06; Number of Contacts:30; Connector Shell Size:18; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Body Style:Straight |
| HM5259405B-75 | Circular Connector; Body Material:Aluminum; Series:PT06; No. of Contacts:30; Connector Shell Size:18; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Circular Contact Gender:Socket; Insert Arrangement:18-30 |
| HM5259805B-A6 | PT 32C 32#20 PIN PLUG |
| HM5264405D | 64M LVTTL interface SDRAM(64M LVTTL接口同步DRAM) |
| HM5264165D | 64M LVTTL interface SDRAM(64M LVTTL接口同步DRAM) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HM5264165 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:HM5264805 HM52654405 Series Synchronous Dynamic RAM |
| HM5264165-10 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| HM5264165A60 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:64M LVTTL interface SDRAM 133 MHz/100 MHz |
| HM5264165B60 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:64M LVTTL interface SDRAM 133 MHz/100 MHz |
| HM5264165D-B60/4805D-B60/4405D-B60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64M LVTTL Interface SDRAM 100 MHz 1-Mword X 1 |
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