- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370621 > HM5264405FTT-75 (Hitachi,Ltd.) 64M LVTTL interface SDRAM 133 MHz/100 MHz PDF資料下載
參數(shù)資料
| 型號(hào)： | HM5264405FTT-75 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 64M LVTTL interface SDRAM 133 MHz/100 MHz |
| 中文描述： | 6400 LVTTL接口SDRAM的133 MHz/100 MHz的 |
| 文件頁數(shù)： | 14/67頁 |
| 文件大?。?/td> | 870K |
| 代理商： | HM5264405FTT-75 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
14
Self-refresh entry [SELF]:
When this command is input during the IDLE state, the SDRAM starts self-
refresh operation. After the execution of this command, self-refresh continues while CKE is Low. Since self-
refresh is performed internally and automatically, external refresh operations are unnecessary.
Power down mode entry:
When this command is executed during the IDLE state, the SDRAM enters power
down mode. In power down mode, power consumption is suppressed by cutting off the initial input circuit.
Self-refresh exit:
When this command is executed during self-refresh mode, the SDRAM can exit from self-
refresh mode. After exiting from self-refresh mode, the SDRAM enters the IDLE state.
Power down exit:
When this command is executed at the power down mode, the SDRAM can exit from
power down mode. After exiting from power down mode, the SDRAM enters the IDLE state.
Function Truth Table
The following table shows the operations that are performed when each command is issued in each mode of
the SDRAM.
The following table assumes that CKE is high.
Current state
CS
RAS
CAS
WE
Address
Command
Operation
Precharge
H
×
×
×
×
×
×
DESL
Enter IDLE after t
RP
Enter IDLE after t
RP
NOP
L
H
H
H
NOP
L
H
H
L
BST
L
H
L
H
BA, CA, A10 READ/READ A
ILLEGAL*
4
L
H
L
L
BA, CA, A10 WRIT/WRIT A
ILLEGAL*
4
L
L
H
H
BA, RA
ACTV
ILLEGAL*
4
L
L
H
L
BA, A10
PRE, PALL
NOP*
6
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
Idle
H
×
×
×
×
×
×
DESL
NOP
L
H
H
H
NOP
NOP
L
H
H
L
BST
NOP
L
H
L
H
BA, CA, A10 READ/READ A
ILLEGAL*
5
L
H
L
L
BA, CA, A10 WRIT/WRIT A
ILLEGAL*
5
L
L
H
H
BA, RA
ACTV
Bank and row active
L
L
H
L
BA, A10
PRE, PALL
NOP
L
L
L
H
×
REF, SELF
Refresh
L
L
L
L
MODE
MRS
Mode register set
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM5264165FTT-A60 | 64M LVTTL interface SDRAM 133 MHz/100 MHz |
| HM5264805FTT-A60 | 64M LVTTL interface SDRAM 133 MHz/100 MHz |
| HM5264405FTT-A60 | 64M LVTTL interface SDRAM 133 MHz/100 MHz |
| HM5264165FTT-B60 | 64M LVTTL interface SDRAM 133 MHz/100 MHz |
| HM5264805FTT-B60 | 64M LVTTL interface SDRAM 133 MHz/100 MHz |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM5264405FTT-A60 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:64M LVTTL interface SDRAM 133 MHz/100 MHz |
| HM5264405FTT-B60 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:64M LVTTL interface SDRAM 133 MHz/100 MHz |
| HM5264405LTT-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SDRAM |
| HM5264405LTT-80 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SDRAM |
| HM5264405LTT-B60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。