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參數(shù)資料
| 型號： | HM5264405FTT-75 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 64M LVTTL interface SDRAM 133 MHz/100 MHz |
| 中文描述： | 6400 LVTTL接口SDRAM的133 MHz/100 MHz的 |
| 文件頁數(shù)： | 31/67頁 |
| 文件大?。?/td> | 870K |
| 代理商： | HM5264405FTT-75 |
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HM5264165F/HM5264805F/HM5264405F-75/A60/B60
31
Write command to Read command interval:
1. Same bank, same ROW address:
When the read command is executed at the same ROW address of the
same bank as the preceding write command, the read command can be performed after an interval of no less
than 1 clock. However, in the case of a burst write, data will continue to be written until one cycle before the
read command is executed.
WRITE to READ Command Interval (1)
CLK
Command
Din
WRIT
READ
in A0
out B1
out B2
out B3
out B0
Dout
Column = A
Write
Column = B
Read
Column = B
Dout
CAS
Latency
DQM,
DQMU/DQML
Burst Write Mode
CAS
Latency = 2
Burst Length = 4
Bank 0
WRITE to READ Command Interval (2)
CLK
Command
Din
WRIT
READ
in A0
out B1
out B2
out B3
out B0
Dout
Column = A
Write
Column = B
Read
Column = B
Dout
CAS
Latency
in A1
DQM,
DQMU/DQML
Burst Write Mode
CAS
Latency = 2
Burst Length = 4
Bank 0
2. Same bank, different ROW address:
When the ROW address changes, consecutive read commands
cannot be executed; it is necessary to separate the two commands with a precharge command and a bank-
active command.
3. Different bank:
When the bank changes, the read command can be performed after an interval of no less
than 1 clock, provided that the other bank is in the bank-active state. However, in the case of a burst write,
data will continue to be written until one clock before the read command is executed (as in the case of the
same bank and the same address).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM5264165FTT-A60 | 64M LVTTL interface SDRAM 133 MHz/100 MHz |
| HM5264805FTT-A60 | 64M LVTTL interface SDRAM 133 MHz/100 MHz |
| HM5264405FTT-A60 | 64M LVTTL interface SDRAM 133 MHz/100 MHz |
| HM5264165FTT-B60 | 64M LVTTL interface SDRAM 133 MHz/100 MHz |
| HM5264805FTT-B60 | 64M LVTTL interface SDRAM 133 MHz/100 MHz |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM5264405FTT-A60 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:64M LVTTL interface SDRAM 133 MHz/100 MHz |
| HM5264405FTT-B60 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:64M LVTTL interface SDRAM 133 MHz/100 MHz |
| HM5264405LTT-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SDRAM |
| HM5264405LTT-80 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SDRAM |
| HM5264405LTT-B60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SDRAM |
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