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參數(shù)資料
| 型號： | HM530281RTT-34 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 331,776-word x 8-bit Frame Memory |
| 中文描述： | 331776字× 8位幀存儲器 |
| 文件頁數(shù)： | 12/47頁 |
| 文件大?。?/td> | 311K |
| 代理商： | HM530281RTT-34 |
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Datasheet Title
12
WE
and
CGW
Input Level, Write Address Pointer, and Data Input State Relationship
WCK Rising Edge
CGW
WE
Internal Write Address Pointer
Data Input
L
L
Incremented
enable
L
H
disable (memory data is retained)
H
Note:
—
Stopped
Data is input when the
WE
input is low.
Read
Read operation:
8 bits of read data are output in synchronization with the RCK clock when the
OE
and
CGR
inputs are low. The access time is stipulated from the rising edge of the RCK clock.
Read reset operations:
When
CGR
is low, by setting
RRS
low, the read address pointer can be set
immediately on that RCK cycle to address 0 and the data will then be output. This operation can be
performed independently of the input level of
OE
. (See ‘Notes on usage’ 14 on the operation when
CGR
is
high.)
Read address pointer increment operations:
The read address pointer is incremented in synchronization
with RCK when
CGR
is low. Data outputs go to the high impedance state when the
OE
input is set high.
The reset address pointer increment function can be stopped by setting the
CGR
input high. This allows
time axis expansion to be implemented easily. (See ‘Notes on usage’ 7, 8 and 10 for interval specifications
of read system reset operations.
*2
)
Note: 2. The read system reset operations stands for read reset, read jump, read window reset, read line
reset and read clear.
Relation Between the
OE
and
CGR
Input Levels and the Read Address Pointer and Data Output
States
RCK Rising Edge
CGR
OE
Internal Read Address Pointer
Data Output
L
L
Incremented
Output
L
H
High impedance
H
L
Stopped
Output data held
H
Note:
H
High impedance
Data is input when the
OE
input is low.
Line Reset (write line reset and read line reset, in 2 dimensional addressing modes)
When the 281R series products are used in 2 dimensional addressing modes, the line length can be set to be
either 1024 dots (2 dimensional (1)) or 1152 dots (2 dimensional (2)). In these modes, after accessing the
相關PDF資料 |
PDF描述 |
|---|---|
| HM530281RTT-45 | 331,776-word x 8-bit Frame Memory |
| HM530281TT-20 | 331,776 WORD X 8 BIT FRAME MEMORY |
| HM530281TT-25 | 331,776 WORD X 8 BIT FRAME MEMORY |
| HM530281TT-34 | 331,776 WORD X 8 BIT FRAME MEMORY |
| HM530281TT-45 | 331,776 WORD X 8 BIT FRAME MEMORY |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HM530281RTT-45 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:331,776-word x 8-bit Frame Memory |
| HM530281TT | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:331,776 WORD X 8 BIT FRAME MEMORY |
| HM530281TT-20 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:331,776 WORD X 8 BIT FRAME MEMORY |
| HM530281TT-25 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:331,776 WORD X 8 BIT FRAME MEMORY |
| HM530281TT-34 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:331,776 WORD X 8 BIT FRAME MEMORY |
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