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參數(shù)資料
| 型號： | HM530281RTT-34 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 331,776-word x 8-bit Frame Memory |
| 中文描述： | 331776字× 8位幀存儲器 |
| 文件頁數(shù)： | 21/47頁 |
| 文件大?。?/td> | 311K |
| 代理商： | HM530281RTT-34 |
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Datasheet Title
21
5. The read address pointer is incremented up to the last address on the line, and then stopped.
Reading is started immediately from the first dot on the next line or the left edge of the window
by execution of the line increment operation.
6. It is possible to move directly from an old window to a new window in window mode by setting up
a new jump address and executing a window setup jump operation. However, the new jump
address should be input after access to the last line of the old window.
7. Read system reset operations (read reset, read jump, read window reset, read line reset and
read clear) and the read address set up operation cannot be executed for consecutive RCK
clock cycles. Similarly write system reset operations (write reset, write jump, write window reset,
write line reset and write clear) and the write jump address setup operation cannot be executed
for consecutive WCK clock cycles.
8. Read system reset (read reset, read jump, read window reset, read line reset and read clear)
operations and read jump address set operations must be performed at times separated by at
least 64 RCK clock cycles. (There is no need to use only 32 word addressing units, and these
operations can be performed on any clock cycle).
9. Write system reset operations (write reset, write jump, write window reset, write line reset and
write clear) must be performed at times separated by at least 64 WCK clock cycles. When
address is input, write/read system reset can not be executed.
10.It is possible to input the write system reset in the middle of 32 word unit addressing. In this
case, not only must the condition of note 8 be met, but furthermore, pairs of write system resets
for units of less than 32 words must be separated by at least 160 WCK clock cycles. When the
write system reset is executed at less than 32 words, the data up to the point to which the
address pointer has advanced will be written, and the remaining data will retain the old values.
(Note that after the completion of a write of less than 32 words, a write reset is required to write
the data for the last address into the memory array.)
11.
Addressing Mode
Address Structure
Input Address
1 dim. add. (FIFO)
0 to 10,367 blocks
Address bit A13 to A0
2 dim. add. (1)
32 horizontal blocks by 324 vertical lines
Line address bits V8 to V0,
horizontal address bits H4 to H0
2 dim. add. (2)
36 horizontal blocks by 288 vertical lines
Line address bits V8 to V0,
horizontal address bits H5 to H0
12.Specifiable window sizes
Horizontal: Between 64 dots and the length of the line.
Vertical: Between 1 line and the maximum number of lines.
13.Location 0 and line end cannot be specified as a jump address. Use a reset to access location
0
.
14.Any number of read system reset operations can be input when
CGR
is high but in this case the
only first reset is effective. This read system reset operation (read reset, read jump, read
window reset, read line reset and read clear) is executed at the rising edge of the RCK just after
CGR
is set low.
15.Any number of write system resets can be input when
CGW
is high, but the only first reset is
effective. This write system reset operation is executed at the rising edge of the WCK just after
CGW
is set to low.
16.When window scan mode is used any case after power on,
WWND
and
WRS
or
RWND
and
RRS
pins are should be input same signal.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM530281RTT-45 | 331,776-word x 8-bit Frame Memory |
| HM530281TT-20 | 331,776 WORD X 8 BIT FRAME MEMORY |
| HM530281TT-25 | 331,776 WORD X 8 BIT FRAME MEMORY |
| HM530281TT-34 | 331,776 WORD X 8 BIT FRAME MEMORY |
| HM530281TT-45 | 331,776 WORD X 8 BIT FRAME MEMORY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM530281RTT-45 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:331,776-word x 8-bit Frame Memory |
| HM530281TT | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:331,776 WORD X 8 BIT FRAME MEMORY |
| HM530281TT-20 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:331,776 WORD X 8 BIT FRAME MEMORY |
| HM530281TT-25 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:331,776 WORD X 8 BIT FRAME MEMORY |
| HM530281TT-34 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:331,776 WORD X 8 BIT FRAME MEMORY |
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