參數(shù)資料
型號(hào): HM621100A
廠商: Hitachi,Ltd.
英文描述: 1048576-word ×1-bit High Speed CMOS Static RAM(1048576字 ×1位高速CMOS SRAM)
中文描述: 1048576字× 1位高速CMOS靜態(tài)RAM(1048576字× 1位高速CMOS SRAM的)
文件頁(yè)數(shù): 7/16頁(yè)
文件大?。?/td> 94K
代理商: HM621100A
HM621100A Series
7
Read Timing Waveform (2)
*1
(
WE
= V
IH
)
t
RC
t
ACS
t
LZ
t
PU
High-Z
50%
Valid Data
t
PD
50%
High-Z
t
HZ
CS
Dout
V
CC
supply
Current
I
CC
I
SB
Note: 1. Address valid prior to or coincident with
CS
transition low.
Write Cycle
HM621100A-20
HM621100A-25
HM621100A-35
Parameter
Symbol Min
Max
Min
Max
Min
Max
Unit
Write cycle time
t
WC
20
25
35
ns
Chip selection to end of write
t
CW
15
17
25
ns
Address valid to end of write
t
AW
16
20
30
ns
Address setup time
t
AS
0
0
0
ns
Write pulse width
t
WP
*2
15
17
25
ns
Write recovery time
t
WR
*3
0
0
0
ns
Write to output in high-Z
t
WZ
*1
0
12
0
15
0
15
ns
Data to write time overlap
t
DW
12
15
20
ns
Data hold from write time
t
DH
0
0
0
ns
Output active from end of write
t
OW
*1
0
0
0
ns
Output hold from address
change
Notes: 1. Transition is measured
±
200 mV from high impedance voltage with Load (B). This parameter is
sampled and not 100% tested.
2. A write occurs during the overlap of a low
CS
and a low
WE
.
3. t
WR
is measured from the earlier of
CS
or
WE
going high to the end of write cycle.
4. Dout is the same phase of write data of this write cycle, if t
WR
is long enough.
t
OH
*4
5
5
5
ns
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