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參數(shù)資料
| 型號(hào)： | HM62832UHP-20 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 256 k High Speed SRAM (32-kword 8-bit) |
| 中文描述： | 256畝高速SRAM（32 KWord的8位） |
| 文件頁(yè)數(shù)： | 8/13頁(yè) |
| 文件大小： | 114K |
| 代理商： | HM62832UHP-20 |
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HM62832UH Series
8
Read Timing Waveform (3)
*1, *2
(
WE
= V
IH
,
OE
= V
IL
)
t
RC
t
ACS
t
CLZ
t
CHZ
CS
Dout
Valid Data
Notes: 1. Transition is measured
±
200 mV from steady state voltage with Load (B). This parameter
is sampled and not 100% tested.
2.Address valid prior to or coincident with
CS
transition low.
Write Cycle
HM62832UH-15
HM62832UH-20
Parameter
Symbol
Min
Max
Min
Max
Unit
Write cycle time
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
OHZ
t
WHZ
t
DW
t
DH
t
OW
t
OH
15
—
20
—
ns
Chip selection to end of write
10
—
12
—
ns
Address valid to end of write
13
—
15
—
ns
Address setup time
0
—
0
—
ns
Write pulse width
*2
10
—
12
—
ns
Write recovery time
*3
0
—
0
—
ns
Output disable to output in high-Z
*1, 4
0
7
0
10
ns
Write to output in high-Z
*1, 4
0
7
0
10
ns
Data to write time overlap
8
—
10
—
ns
Data hold from write time
*6
0
—
0
—
ns
Output active from end of write
*1, 6
3
—
3
—
ns
Output hold from address change
*5
Notes: 1. Transition is measured
±
200 mV from high impedance voltage with Load (B). This parameter is
sampled and not 100% tested.
2. A write occurs during the overlap (t
WP
) to a low
CS
and a low
WE
.
3. t
WR
is measured from the earlied or
CS
or
WE
going high to the end of write cycle.
4. During this period, I/O pins are in the output state so that the input signals of the opposite phase to
the outputs must not be applied.
5. Dout is the same phase of write data of this write cycle.
6. If
CS
is low during this priod, I/O pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
3
—
3
—
ns
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