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參數資料
| 型號： | HM62G36256BP-4 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 8M Synchronous Fast Static RAM(256k-word x 36-bit) |
| 中文描述： | 分同步快速靜態(tài)存儲器（256k字× 36位） |
| 文件頁數： | 10/24頁 |
| 文件大?。?/td> | 137K |
| 代理商： | HM62G36256BP-4 |
HM62G36256 Series
10
Single Differential Clock Register-Register Mode
(M1 = V
SS
, M2 = V
DD
)
HM62G36256
-4
-5
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
CK clock cycle time
t
KHKH
t
KHKL
t
KLKH
t
AVKH
t
DVKH
t
KHAX
t
KHDX
t
KHQV
t
KHQX
t
KHQX2
4.0
—
5.0
—
ns
CK clock high width
1.5
—
1.5
—
ns
CK clock low width
1.5
—
1.5
—
ns
Address setup time
0.5
—
0.5
—
ns
Data setup time
0.5
—
0.5
—
ns
Address hold time
0.75
—
1.0
—
ns
1
Data hold time
0.75
—
1.0
—
ns
1
Clock high to output valid
—
2.1
—
2.5
ns
2
Clock high to output hold
0.5
—
0.5
—
ns
2
Clock high to output valid
(
SS
control)
—
2.1
—
2.5
ns
2, 5
Clock high to output High-Z
t
KHQZ
t
GLQX
t
GLQV
t
GHQZ
t
ZZR
t
ZZE
—
2.5
—
3.0
ns
2, 3
Output enable low to output Low-Z
0.5
—
0.5
—
ns
2, 5
Output enable low to output valid
—
2.5
—
2.5
ns
2, 3
Output enable low to output High-Z
—
2.5
—
2.5
ns
2, 3
Sleep mode recovery time
10.0
—
10.0
—
ns
6
Sleep mode enable time
Notes: 1. Guaranteed by design.
2. Refer to the Test Conditions.
3. Transitions are measured at start point of output high impedance from output low impedance.
4. Output driver impedance updates during High-Z.
5. Transitions are measured
±
50 mV from steady state voltage.
6. When ZZ is switching, clock input K must be at same logic levels for reliable operation.
—
10.0
—
10.0
ns
2, 3, 6
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